FR2542875A1 - Method of addressing the memory in a digital image converter - Google Patents

Abstract

Method of addressing the bulk memory of a digital image converter, in which N points of a radial line specified in polar coordinates after conversion to cartesian coordinates are entered simultaneously in N out of the N<2> storage blocks of the bulk memory 3, these blocks corresponding to N<2> points in a square array of a data block defined in the point-space in question; according to the method, N<2> successive points in the same row of several adjacent data blocks are arranged in N<2> different storage blocks. Application to digital image converters.

Description

MEMORY ADDRESSING PROCESS
IN A DIGITAL IMAGE TRANSFORMER
The present invention relates to a method of addressing the memory in a digital image transformer. It also relates to a device for implementing such a method.

In what follows, using FIG. 1. We will recall what a digital image transformer is.

The essential role of a digital image transformer is to transform an image with relatively slow renewal into an image of the television type and therefore very bright, allowing it to be used in a lighted environment. This slow-renewal image is very generally a radar image, but it can also be images from sonar, infrared sensors, ultrasound systems, which we want to view on screens operating in mode. television. The invention relates more particularly to a digital image transformer associated with radar equipment.

According to FIG. 1, a digital image transformer essentially comprises a circuit 1, called a radar interface circuit which receives the radar video signals VI together with synchronization signals (SY), a coordinate conversion circuit 2, p, 4 of radar video in XY, Cartesian representation on the television screen. Circuits 1 and 2 are connected to a digital memory 3, random access memory (RAM). A remanence circuit 4 is interposed between the radar interface circuit 1 and the memory 3, which is connected to a so-called memory display and read circuit 5. The television monitor 6 is connected to circuit 5.

The functions of the various circuits of a TDI are as follows: - interface circuit 1 samples and digitizes the video signals which are applied to it. It comprises a video compression circuit allowing the acquisition in real time of a radial radar, that is to say the acquisition of the video signals received by this radar after emission of a synchronization pulse SY, for an angle defined antenna, in rotation with respect to a determined origin, and the reading of these video signals, in deferred time and at a different speed, in order to adapt to the access times of the image memory 3, and the unavailability of this memory during the read cycles, which take priority over the write cycles ;; the circuit 2 for converting the polar coordinates into Cartesian coordinates makes it possible to calculate the address of each picture element in Cartesian coordinates from the radar information received in polar coordinates; - memory 3 has a resolution adapted to the television standard used.

It can be for example 1024 lines of 1024 memory cells. Each box corresponds to a point of the image to be displayed. The luminance of each point can be coded for example using 3 bits, allowing 8 levels of luminosity for each point. For this memory, the television reading and radar writing phases are asynchronous. Reading has priority and during a reading phase, the conversion is stopped; the display circuit 5 performs the following operations: generation of television synchronization signals; simultaneous reading of several points of the image memory so as to respect the access times of the circuits used and to allow writing in this same memory; digital to analog conversion of the brightness information read from the image memory to generate an analog television video signal intended for the associated television monitor on which the displayed information appears; - The remanence circuit 4 has the role of restoring for information given in digital, for which the remanence does not exist, a remanence effect comparable to that produced on a memory tube. of a plot begins to decrease as soon as it is entered. The remanence circuit 4 creates a similar effect, however with a delay of one antenna turn and a quantized decrease in level with each turn.

In a digital image transformer, the memory works in time-sharing, part of this time being devoted to writing the incoming information and the rest devoted to online reading of the information that has been stored there. To occupy the memory as little as possible during reading, it is advisable to simultaneously read a maximum number of points per line. As far as writing is concerned, in order to increase its speed, it is desirable to write a maximum number of points simultaneously. This condition is all the more interesting since in a radar associated with the transformer, the renewal of the image is rapid and for certain types of radar, it tends to increase. Currently the speed of rotation of the antenna which gives the frequency of renewal of information is of the order of 5 to 40 revolutions per minute. However, this speed of rotation tends to increase and airfield runway surveillance radars see their speed to reach 60 rpm and higher speeds are even considered.

Currently to be able to operate with radars whose antenna does not turn around 30 revolutions minutes, one writes simultaneously N points of a radial, which-entails for the addressing in X and Y of the cells of the memory, to be able simultaneously register N2 points following a square
The mass memory 3 is composed of memory blocks comprising one or more boxes, each box comprising a certain number of cells according to its capacity. The more cells there are in a shoemaker, the greater its capacity: it is also said that its integration is great.

Currently we have boxes comprising 16 K cells (16x1024) or 64 K cells (64x1024). However, in a digital memory, only one cell can be addressed per set. Carrying out the simultaneous writing of several points requires the use of several boxes.

For reading which is carried out in television scanning, that is to say online, it is only possible to read or address simultaneously only cells arranged in line and contained in different blocks or boxes.

The need to be able to write N2 points simultaneously results in the memory being divided into N2 blocks, each block containing at least one box. However, a block can contain several boxes if they do not have sufficient capacity. In the point-space that can be defined as the set of points constituting the image, N2 points distributed in a square with side N and inscribed in N2 cells constitute what is called a block, each point being "registered" always in the same block of memory. The simultaneous writing of N2 points therefore implies the writing of one point per block in the N2 provided and each point having a determined position in the block considered corresponds in a fixed manner to a block.

The determination of a block in the memory is done by decoding the least significant bits in the addressing in X and in Y. Under these conditions, for two adjacent blocks each consisting of N2 points, two points having the same relative position inside the two blocks have the same Y address, but their X address differs, from one block to another, by one unit for bits of higher rank than those used for decoding inside pavement.

FIG. 2 gives an account of the organization of the space-points broken down into adjacent blocks for which a memory block has been made to correspond to each point of a block, according to a fixed relation in accordance with the prior art. In the example chosen, N is equal to -4, that is to say that the simultaneous registration of 4 points of a radial is carried out. We then consider N2 blocks, that is to say 16 blocks, marked BO to B15 which correspond to the corresponding points of the blocks. The addresses of the points arranged in blocks are entered on the X-coordinate and on the Y-coordinate. Thus the address point X1 (-01) and Y1 (-01) is stored in the block B5. In this figure 2 we have defined 4 adjacent blocks, I, II, III, IV separated by reinforced lines. However, with such an organization we notice that on reading, the number of points that can be read simultaneously is limited to the number of blocks divided by N or when there are several boxes per block, to the number of blocks divided by N and multiplied by the number of boxes per block. Thus in the example chosen for 16 blocks each constituted by a box, corresponding to the use of 64 K boxes for a transformer of definition images 1024 lines by 1024 points, it is only possible to read simultaneously only 16/4, ie 4 points. A quarter of the blocks following a line have interesting information. This is linked, as we have seen previously, to the fact that two points of the same line which have the same relative position in two adjacent blocks are stored in the same memory block, but at a different address. It is not possible to simultaneously read two pieces of information in the same block at two different addresses. This correspondence between the space-points and the memory blocks according to the prior art leads to an increase in the occupation of the memory in the ratio N for reading, when it is desired to carry out the simultaneous writing of N points or N quanta of a radial which requires the possibility of simultaneous writing of N2 points in X, Y square addressing, and a limitation of the performance of digital image transformers. It also involves the use of boxes with a capacity of less than 16 K for a TDI with a definition of 1024 lines by 1024 points with simultaneous writing of at least 4 quanta.

In practice, this solution aiming to use boxes of smaller capacity is not desirable, since the memory thus formed is very large and expensive.

The object of the invention is to remedy this disadvantage which is detrimental to reading by modifying the addressing of the memory.

According to the invention, the method of addressing the memory of a digital image transformer, aimed at increasing the maximum permissible speed of rotation, by the transformer, of the associated radar antenna or of the information sensor, the following method in which a certain number N of points of a radial, identified in polar coordinates and converted into Cartesian coordinates, are simultaneously recorded in the mass memory of the transformer, this memory being constituted by a set of N2 memory blocks, each block comprising one or several memory boxes according to the capacity of said box, each memory block corresponding to a point of each block which comprises N2 thereof in the point space, distributed according to a square of side N, these N2 points of a block being able to be entered simultaneously in different memory blocks, thereby resulting in the simultaneous writing of N points of a radial in N different memory blocks, is characterized in that N2 successive points di placed on a row of the same rank of several adjacent blocks are written in N2 different memory blocks at the same address.

Other advantages and characteristics of the invention will appear in the description which follows, given with the aid of the figures which, in addition to Figures 1 and 2 relating to the prior art, represent:
FIG. 3, the point-space broken down into adjacent blocks for which a memory block according to the invention is made to correspond to each point of a block;
FIG. 4a, a binary addressing word according to the prior art;
FIG. 4b, a binary addressing word according to the invention;
FIG. 5, in schematic form, a device carrying out the modification of addressing according to the invention;
FIG. 6, in schematic form, a device for reading the memory, the addressing of which has been modified according to the invention.

It was indicated in the introductory part of the present application that the simultaneous writing of a certain number of points of a radial, in the digital mass memory of a digital image transformer (TDI) organized in accordance with what is shown in Figure 2, introduced a limitation in the reading phase of this memory, executed line by line according to television mode. This limitation due to the way in which the memory is addressed, to writing, leads to a limitation in the use of a TDI, with radar equipment whose information renewal is rapid, that is to say whose speed of rotation of the antenna is high, currently approaching 60 revolutions per minute and even exceeding them. A digital image transformer is thus characterized by the maximum speed of rotation of the radar antenna that it admits. One then introduces in the TDI, the notion of apparent time of writing of a point in the mass memory. By definition, this apparent time for writing a point in the memory is the average writing time for all the points of a radial. It depends on the access time to the memory, the occupation of this memory for reading in television mode and the number of points or quanta of the radial written simultaneously.

toursiminute
Dans ces conditions, un transformateur d'images n'ayant pas de direction privilégiée, les radiales couvrant toutes les valeurs d'angle par rapport à une fréquence donnée pour être certain d'écrire simultanément au moins N points d'une radiale, il est nécessaire de pouvoir écrire N points simultanément en coodonnées cartésiennes. L'écriture simultanée de N2 points implique un nombre de registres tampons d'adresses et données égal à N2.Ces tampons, 24, sont visibles sur la figure 5 qui donne une présentation schématique du dispositif d'inscription de N points d'une radiale pour N = 4.te being the apparent writing time of a point, the maximum conversion time tc of the points of a radial of the polar coordinates in which they are collected, into Cartesian coordinates in which they are recorded in memory is tc = te x 1024 x A / 2 for a memory definition of 1024 points by 1024 lines. The factor ~ is introduced by the fact that the maximum conversion time is relative to the radial coinciding with the diagonal of the associated television monitor screen.
If 4096 radials are converted during one antenna revolution, the maximum rotational speed allowed by the digital image transformer is

round
Under these conditions, an image transformer not having a privileged direction, the radials covering all the angle values with respect to a given frequency to be certain of simultaneously writing at least N points of a radial, it is necessary to be able to write N points simultaneously in Cartesian coordinates. The simultaneous writing of N2 points involves a number of address and data buffer registers equal to N2. These buffers, 24, are visible in figure 5 which gives a schematic presentation of the device for writing N points of a radial for N = 4.

The time necessary for writing is thus divided by N but not the apparent writing time because it depends on the correspondence between the point space and the memory blocks constituting the corresponding memory which influences the reading time and therefore on the time available for writing, memory operating in timeshare for writing and reading. The memory 3 is thus divided into N2 identical blocks 300 to 315 so as to allow the simultaneous writing of at least
N points of the same radial. However, as has already been said, this breakdown into blocks has a limit, depending on the integration of the memory units chosen and the desired definition.

We currently have 16K x Ibit boxes and 64K x 1 bit boxes. For a definition of 1024 lines by 1024 points, the maximum number of blocks will be 64 with 16 K x 1 bit boxes or 16 with 64 K x 1 bit boxes. In any case, the number N2 of blocks is less than or equal to the number of boxes. The apparent writing time depending among other things, as seen above, on the occupation of the memory considered for reading on television, the number of points N2 that can be read simultaneously depends on the number of memory boxes
N3, itself depending on the desired definition and the capacity of the boxes chosen, as well as the memory organization in writing. If in the N3 boxes chosen we want to be able to write N2 points simultaneously following a square addressing, allowing the simultaneous certain writing of at least N points resulting from the conversion of at least N quanta of the radial considered, the number of boxes that can have information on the same line becomes

The apparent writing time is given by te - tw
- # (1) formula in which tw is the time taken by writing to the memory, given by the manufacturer of the memory boxes,
NOT ; the number of points of a radial that can be written simultaneously.

P; memory occupation by reading.

formule dans laquelle Np représente le nombre de lectures par ligne, TR la durée d'un cycle de lecture, qui est constante suivant les mémoires choisies,
Tp la durée d'une ligne télévision, qui est une constante dépendant du standard télévision choisi.This memory occupation time by reading is expressed by

formula in which Np represents the number of readings per line, TR the duration of a read cycle, which is constant according to the memories chosen,
Tp the duration of a television line, which is a constant depending on the television standard chosen.

In these conditions

comme cela a déjà été défini.formula in which
N1 is the number of points on a line, a constant which depends on the desired definition, 1024 points for example.
N2 the number of points read simultaneously.
It follows that

as has already been defined.

The number N2 of points read simultaneously thus corresponds to the number of boxes that can have information on the same line when it is desired to simultaneously write N points of a radial considered.

The number N3 of boxes is moreover a constant depending on the integration of the boxes chosen. It was noted that the number of boxes was 16 for random access memories of 64 K × 1 bit and a definition of 1024 points × 1024 lines.

avec

It has been noted that N being the number of points of a radial that can be written simultaneously, in square addressing, the number N2 is less than or equal to N3.
Using formula 2, we have

with

C being a constant.
The apparent writing time becomes

According to this equation, we see that the simultaneous writing of N points is only interesting if N (1 - CN)> 1 that is to say if C <for N 4. Under these conditions indeed, the time of apparent handwriting may be decreasing.

Thus to simultaneously write a number N of points of a radial and meet the condition stated above of C less than 1/4, it is necessary to seek a compromise between the integration of the memory boxes used and the performance of the image transformer. .

For a definition of 1024 lines x 1024 points and a television standard of 50 Hz with interlacing of the lines, with - 16 K x 1 bit memory units displaying a duration of 200 ns for a cycle of 1024 200 ns reading, we have C = 64 x 35.6 ns u 0.09. With 64 K x 1 bit memory units, we have C = 0.36> 0.25. According to the prior art, the acceptable compromise entails the use of 16 K × 1 bit memory units which do not correspond to the maximum possible integration.

For a number N = 4 of points of a radial to be written simultaneously, the apparent writing time becomes te = tw with 16 K x 1 boxes. Under these conditions, it will be noted that, for boxes of lower capacity, the maximum admissible speed of rotation Vm is reduced compared to that which one would have by entering a single point. In this case, in fact, the apparent writing time is equal to you tw = tw = tw. The
1-c 1-0.09 0.91 observed decrease in the maximum permissible rotational speed is 2.56 0.91 = 2.81. This value shows that the simultaneous writing of 4 points of a radial is then not optimized, since the theoretical reduction should be 4.

FIG. 2 shows the correspondence, according to the prior art, between the point-space and the memory blocks, more particularly between the space-
points broken down into adjacent blocks each grouping N2 square points and N2 memory blocks of memory 3. This figure was described in the introductory part of the present application, it will not be repeated here.

FIG. 3 schematically shows the correspondence, according to the invention, between the point-space broken down into adjacent blocks, here, 4, since N = 4 has been chosen as a non-limiting example for the description, each block grouping together N2 (16) square points and N2 blocks of digital mass memory 3, following the modification of the addressing, object of the present invention.

According to FIG. 2 relating to the prior art, the choice of the blocks for the points of the block was identical from one block to another, resulting in that for a line along which the reading was made, there were N2 successive points of the row, arranged in N blocks with N different addresses, requiring N memory accesses; a waste of time ensued, since as has been explained, only 1 block out of N, that is to say according to Example chosen 1 block out of 4 contained interesting information for each reading. According to the addressing according to the invention, N2 successive points of a line are found stored in the N2 blocks of the memory in such a way that when reading, done in television mode, all the blocks hold information. The invention therefore, the addressing is such that for a given line li of a block, the points of which are characterized by the same address in Y, the information is entered in the blocks used to store the information of the line li + 1, from the previous adjacent block. The row index i + 1 is obtained by a modulo N addition, that is to say that for N = i, N + 1 = 1.

This previous adjacent block is made up of N2 points and two points having the same relative position inside the considered block and the previous block have the same Y address but the X address of the previous block is that of the considered block minus one unit for them. addressing bits in X, removing those used for decoding inside the pave.

The modification of addressing, according to the invention, thus consists in carrying out a permutation in the selection of the blocks of a block along the lines of the adjacent blocks.

Thus, by way of example, referring to FIG. 3, if 11, 12, 13, and 14 denote lines of blocks, it can be seen that line 11 of block II is stored in the same blocks as line 12 of block I, that line 11 of block III is memorized in the same blocks as line 12 of block II and that line 11 of block IV is memorized in the same blocks as line 12 of block III.

Likewise, line 12 of block II is memorized in the same blocks as line 13 of block I, line 12 of block III is memorized in the same blocks as line 13 of block 11 and line 12 of block IV. memorize in the same blocks as line 13 of block III. The same is true for lines 13 of blocks II, III, IV which are stored respectively in the same blocks as lines 14 of blocks I, II, III. Lines 14 of blocks II, III and IV are stored in the same blocks as lines 11 of blocks I, - II, III. This is indeed a modulo N permutation.

In what follows, we will explain how this modification of the addressing of the digital mass memory of the digital image transformer is carried out, for the simultaneous recording of N points of a radial, allowing the simultaneous reading of N2 points in line.

FIG. 4a represents the binary word for addressing a point according to the prior art. This word has 4 addressing fields. The field A, of value a containing the least significant bits along the X coordinate allowing decoding along the X abscissa of the memory block, the B field of value b containing the least significant bits along the Y coordinate , allowing decoding according to the Y coordinate of the memory block. These two fields A and B therefore make it possible to obtain the designation of the memory block in which a point among
N2 of a paving stone. Fields A and B are sufficient to decode a memory block. However, two other fields have been added to the A and fields.

The field C, of value-c containing the addressing bits in X of weight immediately greater than that of the least significant bits of the bits of the field A, allowing decoding along the abscissa X of the block containing the point considered among N blocks . The field D, of value d constitutes the complement of addressing such that the set of fields C and D gives the address of the point in the block which has been selected.

FIG. 4b represents the binary word for addressing a point according to the invention. This word has 4 addressing fields A, B, C and D like the previous one. The field A containing the least significant bits in X of value a is not modified with respect to the previous one, it allows decoding along the abscissa of a memory block. The field B, of value b + c is modified, according to the invention, becoming the sum of the preceding address fields B and C and making it possible to decode Coordinate of the memory block considered with the permutation as described previously for the choice of memory blocks according to the lines of the adjacent blocks. The combination of the new fields B and A makes it possible to select for N2 points located on the same line, N2 different memory blocks.The fact of taking for field C, of value b the old field B makes it possible to have in addition, the N2 points contained in the N2 blocks, at the same address. The field D of value d is kept without modification.

FIG. 5 represents in schematic form a device carrying out the modification of addressing made according to the invention.

The circuit 2 for converting the polar coordinates into Cartesian coordinates comprises two circuits 21 and 22, accumulators, respectively receiving the quantities sin G and cos 4. The accumulator circuit 21 makes it possible to obtain the abscissa of the points identified in polar coordinates by performing the sequence of operations XN = XN-1 + sin 4, N being the number of accumulations. The determination of the abscissa X in car tesian coordinates is therefore done by iteration. The accumulator is triggered by a processor, not shown, which manages the angles identifying the radials with respect to a determined origin. The original value of the conversion is that corresponding to the entry point on the screen, the value at which the operation of the accumulator ceases is that corresponding to the output of the screen, or the end of the radial. The accumulator circuit 22 operates in the same way as the circuit 21, to give the ordinate of the points considered. It performs an iteration operation YN = 'YN 1 + cos 8. Circuit 23 provides the addressing of the video compression memory located in interface circuit 1. The accumulators 21 and 22 respectively deliver the coordinates X and Y points to be written into the memory in digital form, the X coordinate comprising for example 10 bits xg to x0, the Y coordinate also comprising for example 10 bits, yg to y0.

The least significant bits of the X coordinate, that is for example the two bits x1, x0, making it possible, as has already been noted, to choose the abscissa of the block in the memory, are applied to the decoder 26 allowing the abscissa to select the memory block chosen by means of the associated buffer register 24. In the example chosen of N = 4, these registers are 16 in number, 2400 to 2415.

On the other hand, to produce the field B of the digital addressing word of FIG. 4b which, according to the invention, carries the information, sum of the values b and c, the least significant bits of the Y coordinate, i.e. Y1 and y0 and the most significant bits immediately greater than the least significant bits xl, x0 of the field A, i.e. the average significant bits x and x25 are added binary in circuit 25 and are applied to decoder 26 allowing the ordinate to select the memory block chosen by its associated buffer register with the modulo N shift for the lines of the adjacent blocks. The output S1 thus allows the selection of the memory block. This binary addition effectively performs the permutation of the lines of a block along the lines of the previous adjacent block.

Thus, if one considers, in FIG. 3, the point of the block II which was stored in the block Bo, it is stored in the block B4 by application of the method for modifying the address according to the invention.

address field A of # value a following X: 00
address field B of value (b + c) following y: 0O + 01 = 01.

The set of addresses 00 and 01, respectively along the abscissa
X and the ordinate Y designates the block B4.

Likewise, if one considers, in FIG. 3, the point of block II which was stored in block B7, it is stored in block 811 by applying the method for modifying the address according to the invention:
address field A with value a following X: 11
address field B of value b + c following Y: 01 + Ol = 10
The set of addresses 1 1 and -01, respectively along the abscissa
X and the ordinate Y designates the block B11.

The decoding in circuit 26 of the address fields B and A allows
to select a buffer register 24 in which the address is stored
write inside the block and the corresponding data. The registers
buffers 2400 to 2415 have an ad address part and a
given do. The write address inside the selected block is
composed of the field D, comprising the address bits x9 to x4, yg to y2 and the
field C, or according to the invention, the old field B comprising the bits
of low order address yl, y0 'allowing to have N2 points of the same line, always stored in N2 blocks with the same address in y (yg to y0)
constant for a line and in X (xg to X4) constant for the 16 points
considered on a line, in the case where N = 4.

The data parts dO of the buffer registers 2400 to 2415 receive
of circuit 1, by conductor 241, the compressed video information. The
video compression circuit, located in the interface circuit had been
originally addressed by circuit 23. Triggered by the initia command
lisation, triggering the conversion circuit 2, that is to say giving the
X0, Y0 value of the entry point on the TV monitor screen and
receiving the increment command inc, the circuit 23 controls the
video compression circuit for obtaining compressed video
corresponding to the points considered.

FIG. 6 schematically represents the reading device
digital mass memory 3, addressed in accordance with in
vention. This reading device allows you to view the information read
in memory 3, on the associated television monitor 6.

An oscillator 27 generating the frequency of the triggered television point
che the synchronization generator 28 supplying the television monitor 6. Oscillator 27 also controls a generator 29 delivering the read addresses of memory 3, through an operator 40 which regulates the time-sharing operation of memory 3 for writing and reading, these two phases being asynchronous with, however, the priority reading phase. The oscillator 27 also controls the generator 29 of the read address signals from the mass memory; the maximum number of points per read cycle is read to reduce the memory occupation. The number of points read in a single reading is equal to the number of memory blocks multiplied by the number of boxes per block in the case where there are several, as explained previously. However, for reading, the weights of addressing of adjacent tiles are replaced by the bit weights used for decoding the lines of the tiles. The least significant bits yl, y0 then replace the bits x3, x2 in the addressing of the memory. The N3 points which have been memorized on writing are stored in a buffer register 44 connected to the mass memory. In this buffer register 44, the luminance values of the N3 points are written in binary form, for example with 3 bits. It will be recalled that according to the invention which modifies the addressing of the memory during writing, two points having the same abscissa, - on the same line of two adjacent blocks, are not stored in the same block of the memory, but in two different blocks. The addressing of the buffer register 44 in which the N3 points read from the memory have been stored is done in accordance with the write addressing. The modification of the addressing which must be carried out is made in the adder circuit 43 connected on the one hand to the buffer register 41 which stores the two least significant bits yl, y0 of the Y address of the points to be read, and d 'on the other hand to circuit 42, for addressing the points in television scanning, a circuit which transmits bits # 3' x2 of the address in X. According to the selection made by the two bits of the output of adder 43 and the two bits x1, x0 given by the circuit 42, the buffer register 44 thus outputs a digital video signal which is converted into an analog signal in the transformer 45. This signal is then transmitted to the television monitor, together with the output synchronization signal. by generator 28.

A method and a device for addressing the digital memory of a digital image transformer have thus been described.

Claims (7)

1. Method of addressing the memory of a digital image transformer, aimed at increasing the maximum speed of rotation, admissible by the transformer, of the associated radar antenna or of the information sensor, method according to which a certain number N of points of a radial, identified in polar coordinates and converted into Cartesian coordinates, are simultaneously entered in the mass memory of the transformer, this memory consisting of N2 memory blocks, each block comprising one or more following memory units the capacity of said box, each memory block corresponding to a point of each block which comprises N2 thereof in the space-points, distributed according to a square of side N, these N2 points of a block being able to be written simultaneously in different memory blocks, resulting in therefore the simultaneous recording of the N points of a radial in N different memory blocks, characterized in that N2 successive points arranged on a line of the same rank of several adjacent blocks are written in Nc different memory blocks at the same address. 2. Method according to claim 1, wherein the space-points being divided into blocks consisting of N2 points, a point of a block being stored in a memory block and the correspondence between the N2 points of a block and the N2. memory blocks being such that the position of a point in a block is given by the least significant address bits in X and Y, and that the position of a block in point space is given by the d bits 'address of greater weight, characterized in that, for N2 successive points of a row of the same rank of several adjacent blocks, the choice of a memory block for a point of a block is determined from the row of rank immediately above the preceding adjacent block. 3. Method according to one of claims 1 or 2, characterized in that, for a given line li of a block whose points are characterized by the same address in Y, the information is entered in the blocks of the line. li + 1, modulo N, of the previous adjacent block in which the information had been stored. 4. Method according to claim 3, wherein the addressing word comprises an addressing field A of value a containing the least significant bits along the X coordinate, an addressing field B of value b, containing the bits of least significant according to the Y coordinate, an addressing field C of value c containing the addressing bits in X of weight immediately greater than those of the field A, allowing decoding along the abscissa X of the block containing the point considered among N blocks, and an addressing field D of value d constituting the addressing complement, characterized in that, in the addressing word, the fields A and D are kept and that the fields B and C are modified, the field B displaying a value b + c allowing the decoding according to the ordinate Y of a memory block, allowing to have N2 points of a line contained in N2 different blocks, the field C displaying a value b which, associated with the value d of the field D, constitutes the addressing complement, making it possible to have the N2 points of a line stored at the same address in N2 different blocks. 5. Method according to one of claims -1 or 4, wherein the reading of the memory is done online following a television scan, characterized in that the number N3 of the points read in a single reading is equal to the number of blocks. memory multiplied by the number of units per block, the memory address of the N3 points being modified in accordance with what is done for writing, taking as the address value of the field C, the value b, all the fields address C and D giving the address of the points inside the blocks, the selection of a point among N2 of the N3 points read, being modified, in accordance with the modification made for the selection of the writing blocks, by performing the decoding of the addressing fields B and A of value b + c and a respectively. 6. Device for addressing the mass memory of a digital image transformer implementing the method according to all of claims 1 to 4, comprising a radar interface circuit, a circuit for converting the polar coordinates into Cartesian coordinates, a digital mass memory, a remanence circuit, and a decoder circuit, characterized in that it comprises inserted between the coordinate conversion circuit (2) and the mass memory (3), an adder circuit ( 25), carrying out the modification of the address field B by carrying out the addition in binary of the least significant bits (y1, y0) of the address following the ordinate Y, and of the higher order bits (X3, x # of the address following the abscissa X. 7. Device implementing the method according to claim 5, comprising for reading the points written in the memory blocks, an oscillator (27) of the television frequency, connected to a synchronization generator (28), to a generator (29). ) read addresses from the memory (3), and to a circuit (42) for addressing television points, a digital-to-analog transformer (45) and a television monitor (ó), characterized in that it comprises a addition circuit (43) in binary of the least significant bits (Y1, y0) of the memory read address following the ordinate Y, coming from the memory read address generator (29), through a buffer circuit (41) and higher order bits (x3, x2) of the next address X delivered by the television point addressing circuit (42), the output of said adder circuit (43) allowing with the bits of Least significant addressing in X (xl, x0), delivered by circuit 42, to select a point among the N3 in. ints contained in the buffer circuit (44) and simultaneously read from the memory.