FR2538615A1 - Method of manufacturing bipolar integrated circuits with dielectric insulation and integrated circuits thus obtained. - Google Patents

Abstract

The integrated circuit obtained includes at least one compartment, completely surrounded by silicon oxide 3, 7, resting on a doped monocrystalline silicon substrate 1 and containing doped silicon, with conduction type opposite that of the substrate, in which a component is manufactured with conventional bipolar technology. According to the invention, the following steps are undertaken, on one same previously polished face of the substrate: a localised oxidation 3 is carried out locally, with LOCOS technology to form the bottom of the compartment; an epitaxial layer of doped silicon of a first type of conduction 6 is grown; a recrystallisation of the epitaxially grown layer is carried out by heating with scanning; the walls 7 of the compartment are produced using LOCOS technology. Application: production of integrated circuits containing transistors whose electrical insulation is improved.

Description

METHOD FOR MANUFACTURING INSULATED BIPOLAR INTEGRATED CIRCUITS
DIELECTRIC AND INTEGRATED CIRCUITS THUS OBTAINED.

 The invention relates to a method of manufacturing bipolar integrated circuits with dielectric insulation comprising at least one box whose walls and bottom are formed by a layer of silicon oxide, said box resting on a substrate made of silicon and containing monocrystalline silicon doped with a first type of conduction in which a component is manufactured according to conventional bipolar technology.

 The invention also relates to integrated circuits obtained by implementing the method.

 In the technique for producing bipolar integrated circuits, there is the general problem of electrically isolating the various components of the circuit produced on the same wafer of semiconductor material, in particular silicon. To obtain this electrical insulation, there are two known means, which are isolation by junction (reverse polarized P-N junction) and isolation by dielectric. The first means, although the most generally used up to now has the disadvantage of introducing parasitic capacitances, of causing parasitic leakage currents on the substrate for saturated transistors or the risk of unblocking the PN junction normally reverse biased in the event of overshoot in the circuit, for example. The dielectric isolation technique is more efficient but also more complex and therefore more expensive to implement. The so-called EPIC technique offered for fifteen years by the American company MOTOROLA and also marketed by the American company HARRIS, consists in having a dielectric layer, in this case silicon oxide SiO2, around each component over the entire surface of the wafer so as to constitute perfectly insulating boxes. To do this, we start from an N-type plate in which a selective etching is carried out which defines the walls of the boxes and a layer of insulating SiO2 is added. Next, a gas phase deposition of polycrystalline silicon of several hundreds of microns thick which has only a mechanical strength role. Then, by abrasion, silicon type N is used, until it is flush, in the grooves, with polycrystalline silicon. We see, by turning the wafer, that we have created insulated boxes by dielectric. The main difficulty of this technique lies in the fact that it requires operations on both sides of the wafer and that it is difficult to obtain good parallelism between the lapped face and the bottom of the boxes in particular. This technique, which is rather delicate to develop and relatively expensive, is not widely used, despite its certain advantages from the point of view of electrical performance. It will also be noted that it is not generally essential to isolate by dielectric wall boxes all the components of a circuit arranged on the same integrated circuit board but only a certain number of these components (certain NPN transistors likely to enter saturation for example).

 We also know a process called Isoplanar, intermediate between the isolation by junction and the EPIC technique: the bottom of the box corresponds to an isolation by reverse polarized junction and the walls are insulated thanks to oxide walls.

 An object of the present invention is that the continuation of the operations necessary for the implementation of the method is carried out on the same face of the silicon wafer, so as to combine certain advantages of the two known methods described above.

Another object is to produce on a silicon wafer boxes fully insulated by dielectric, by a succession of localized oxidation
Yet another object is to be able to combine on a silicon wafer boxes fully insulated by dielectric, boxes fully insulated by junction and boxes whose walls are insulated by dielectric and the bottom insulated by junction.

 Yet another object is to be able to produce PNP vertical transistors and NPN vertical transistors on a silicon wafer, each transistor being entirely isolated by dielectric.

These aims are achieved and the aforementioned drawbacks of the prior art are mitigated by the fact that the method defined in the preamble is characterized by the following series of operations all carried out on the same previously polished face of the substrate - A monocrystalline silicon substrate of second type of con
duction is locally oxidized, using LOCOS technology, on
an area delimited so as to constitute the bottom of said box.

- An epitaxial layer of sili is grown on the substrate
doped cium of the first type of conduction.

- We recrystallize the epitaxial layer by
heating with sweeping.

- The walls of the said wall are produced using LOCOS technology
box.

 During the growth of the epitaxial layer, polycrystalline silicon is formed above the oxidized zone intended to constitute the bottom of the box, while monocrystalline silicon is formed elsewhere. The heating technique with scanning at the limit of the fusion of the silicon as for the realization of MOS transistors according to the SOI technology allows a recrystallization of the polycrystalline silicon, facilitated by the presence of a certain amount of monocrystalline silicon which surrounds the localized part of polycrystalline silicon and which thus serves as a germ.

A first preferred embodiment of the method according to the invention is remarkable in that the walls of said box are produced in two stages after the bottom of the box is made of silicon oxide - The first stage consists in causing the substrate to crol
first thin epitaxial layer of doped silicon of the first type
conduction, to recrystallize the layer
epitaxially heated by sweeping and to be produced by
LOCOS technology the lower part of the walls of said cais
his.

- The second step is to grow on the first layer
epitaxial a second epitaxial layer of silicon- doped with pre
mier type of conduction with a thickness between 0.4 and 0.95
times the depth of the box, and to be done using tech
LOCOS nology the upper part of the walls of said box.

In bipolar technology, the depth of the caissons is of the order of 10 μm and it can be quite long, even with the LOCOS technique, to obtain oxide layers of this thickness for producing the walls of the caisson. On the other hand, if one proceeds in two stages as indicated above, the thicknesses to be reached are reduced substantially by half, for the production of the walls, and thus become usual for the technique.
LOCOS, which implies an overall time saving compared to the process which consists in producing the walls in a single deep oxidation. In addition, the two-stage process allows, if necessary, to realize PNP vertical transistors, assuming that the substrate is of type P, as is the case in conventional bipolar technology, by making a diffusion P at the bottom of the box which is previously constituted by a part of the first epitaxial layer of type N.

 The fact of starting from a P-type substrate also makes it possible to marry the conventional bipolar technology with isolation by total or partial junction (the walls only of certain wells can be produced in the form of Sio2) with the dielectric isolation process proper according to the invention.

 The description which follows, with reference to the accompanying drawings, all given by way of example will make it clear how the invention can be produced, all the figures showing a partial section of an integrated circuit board.

 FIG. 1 represents in a, b, c, d, e, five successive stages for the implementation of a first embodiment of the method according to the invention.

 FIG. 2 represents a second embodiment of the invention.

 FIG. 3 represents a variant of the second embodiment of the invention.

 FIG. 4 represents, according to the second embodiment, different possibilities offered by the invention for the production of integrated circuits.

 In the figures, the same references designate the same elements with the same functions.

Figure la shows in 1 a monocrystalline silicon wafer doped with a certain type of conduction acting as a substrate. To fix the ideas, it is assumed in the following text that the substrate is of the P conduction type which is moreover usual in the technology of bipolar integrated circuits. The method according to the invention aims to form a box whose walls and bottom are formed by a layer of silicon oxide by a series of operations carried out on the same face of the substrate. To this end, one face 2 of the substrate 1 is polished so as to obtain an optical polish. The bottom of each box is then produced, as shown in FIG. 1b, in the form of a localized layer of silicon oxide whose surface corresponds to that desired for the box and whose thickness is of the order of To obtain this high thickness, we preferably use the technique known as LOCOS, used in particular by the French company RTG and more generally by the Dutch company PHILIPS, especially for the production of NOS structures. This technique consists in first depositing a thin layer of nitride, -Si3N4 on the entire wafer; this thin layer is then photograved with precision at the locations chosen for the diffusions; it is then possible to grow thick layers of SiO2 on the silicon thus exposed and to remove the residual nitride layers. Improvements have been made to the technique
LOCOS indicated above: to obtain better adhesion of the nitride layer, provision may be made to cover the substrate, before deposition of the nitride, with a very thin layer of silica. On the other hand, the generation of thick silicon oxide causes swelling of the oxidized zone. To obtain good final flatness of the treated surface, one means consists, after pickling of the nitride layer at the places to be oxidized and before oxidation, at etching the silicon at these places to a depth equivalent to 10 to 20% of the thickness of the oxide layer to be created. The LOCOS technique is made possible by the fact that there are selective strippers, some attacking the nitride and not the oxide, others, on the contrary, attacking the oxide without attacking the nitride. By using this technique, therefore obtains on the side -2 of the wafer oxidized zones at predetermined locations as shown in 3 in Figure 1b for a box. Oxidation is generally carried out in high temperature ovens at different speeds depending on the process used. Dry heating with oxygen can be used or operating in the wet phase, in the presence of water vapor.

 Next, a layer referenced 4, FIG. 1c, of silicon doped with a conduction type opposite to that of the substrate is grown by epitaxy on the face 2 of the wafer, ie, in accordance with the example chosen above, an epitaxial layer. type N.

By taking the usual conventional precautions in bipolar technology, it is thus possible to obtain a quality monocrystalline LI layer above the non-oxidized part of face 2 of the substrate.

Above the oxidized zones 3, on the other hand, twins and, in general, polycrystalline silicon can form, which is indicated by the zone 5 identified by crosses in FIG. 1c. Zone 5 has a lateral offset due to inline lines which correspond to the general crystalline orientation of the layer LI, Zones 5 are obviously unsuitable for implanting a component, for example a transistor for which a monocrystalline material is absolutely necessary.

An essential characteristic of the invention is to reconvert the zones 5 into monocrystalline silicon, all other things being equal, as shown in FIG. A known method for obtaining this result is described for example in the publication "Electronics review" of June 2, 1982 pages 115 and 46 in two articles, one by J.ROBERT LINEBACK, the other by RODERIC
BERESFORD. This process, used in particular by the American firm
Texas Instruments Inc. is intended for the manufacture of C-MOS integrated circuits and known as the SOI process (Silicon On Insulator in English) called to compete with the SOS process (Silicon On Sapphire in English). process in question consists in producing a monocrystalline silicon wafer of which one face is covered with a layer of silicon oxide with the exception of a strip at the edges constituted by monocrystalline silicon, then in covering this face a thin layer of polycrystalline silicon with a thickness of approximately 0.5 μm. The wafer thus produced is placed, under an argon atmosphere, in an oven whose temperature is adjusted slightly below the silicon melting temperature. A heating strip, for example made of graphite, then scans the surface of the wafer to be recrystallized at a predetermined small distance above the latter. The slight temperature increase provided by the heating strip and the relative movement between the wafer and the heating strip are such that the part of the polycrystalline layer located directly above the heating strip is just melted, which, from the seed formed by the edges of the wafer, allows progressive recrystallization of any superficial polycrystalline layer. On the other hand, the molten part at a given instant of this surface layer is thin enough to be held in place by the effect of surface tension with respect to the neighboring parts of the wafer which have remained or become solid again. Instead of the graphite heating strip, a laser, electron beam or lamp device can also be used. The recrystallization process described above must, for the implementation of the invention, be adapted to thick sors of polycrystalline silicon about twenty times greater.

This adaptation does not pose any particular problem to those skilled in the art who, in this matter, can play on several parameters, such as the nature of the additional heating and its distance from the plate, the relative speed of movement and / or the intensity of the means. of additional heating and which, moreover, knows the conventional methods of drawing silicon crystals and the methods using zone fusion used for the crystallization of a polycrystalline silicon ingot. # as a localized oxidation of the substrate as is the case according to the present invention, the recrystallization of the surface polycrystalline layer is facilitated by the presence of numerous monocrystalline silicon seeds between the different wells to be created in the silicon wafer .

 It is thus possible to obtain an epitaxial layer 6, FIG. 1d, of entirely monocrystalline silicon on the face 2 of the substrate.

 The last operation of the method according to the invention consists in generating silicon oxide walls 7, FIG. 1 a, preferably by means of LOCOS technology. The procedure described with reference to FIG. 1 makes it possible to obtain boxes completely surrounded by thick silicon oxide in which everything that is made possible by means of the EPIC technique for the implantation of components in these boxes. is also in competition. The areas of the wafer which do not contain silicon oxide are identical to the usual supports used in bipolar technology (P-type monocrystalline substrate covered with a layer of N-type monocrystalline silicon) and therefore allow the known implantation of components. insulated by junction.

If it is necessary to implant buried layers, this is possible, by diffusion, just before the deposition of the epitaxial layer 4, FIG. 1c.

 The LOCOS process makes it possible to obtain thick layers of silicon oxide. However, the speed of oxidation decreases with the depth to be reached and it can be long and therefore expensive to obtain thicknesses of the order of 10 μm for the production of the walls of the caissons.

 To overcome this drawback, a second embodiment of the invention described below with reference to FIG. 2 consists in building the walls of the box in two stages: the first stage is similar in all respects to the method of FIG. 1, with the difference that the epitaxial layer of silicon, referenced 8 has a reduced thickness. The second step consists in growing, still on the same side of the wafer, a second epitaxial layer 9 of the same type of conduction as the first. The only places in this epitaxial layer comprising polycrystalline silicon are the zones 11 which are located at the level of the oxidized parts of the layer 8, that is to say at the level of the edge of the caissons.

A recrystallization of the second epitaxial layer is therefore not essential and to complete the construction of the walls of the caissons already started at 12 in the first epitaxial layer, it suffices to practice a second deep oxidation, in the polycrystalline silicon parts 11 by means LOCOS technology or by ion implantation using the same mask which was used to make the oxidized parts 12 or an equivalent mask, until the parts 12 are reached. The second embodiment has other advantages than that of a easier realization of the walls of the boxes by the LOCOS process. It allows to obtain, in a simple way and moreover known per se, a buried layer of the type
N + for the production of quality NPN transistors, by means of growing a first epitaxial layer of type N +, as shown in 13 in FIG. 3. Furthermore, the two superimposed epitaxial layers can be of uneven thickness provided that the sum of these thicknesses is equal to the desired depth for the boxes. It is for example possible to produce a first epitaxial layer of small thickness, of 0.5 vm for example, in order to facilitate the recrystallization of the polycrystalline silicon situated above the oxidized zone 3.

The second embodiment and its variant (Figures 2 and 3) also allow the production of good transistors
Vertical PNP as shown in FIG. 4 in 111: after deposition by epitaxy of layer 8 of type N, recrystallization and constitution of the lower part of the walls by the LOCOS process, the bottom of the box is transformed into a monocrystalline zone 10 of the type conduction P by diffusion of trivalent impurities, after which the process for constituting the wells is continued according to the second embodiment.
Vertical PNP 14 it is sufficient to create by diffusion a surface layer 16 of type P for the transmitter (respectively the collector) and, separated in the same box, a deep diffusion 17 of type P which penetrates into zone 10 to obtain a setting of collector (respectively of transmitter) constituted by zone 10.
It will be noted that the constitution of PNP vertical transistors such as 111 is compatible with that of conventional vertical NPN transistors such as 15. To make the transistor 15, it is possible, as an option, to diffuse an N + buried layer at the bottom of the well in the epitaxial layer 8 then, when the box is finished, make two nested diffusions in the second epitaxial layer 9, one of base 18 of type P, the other of emitter 19 of type N +. The collector of transistor 15 is constituted by the part bottom of layer 9, by layer 8 optionally N + doped and may include, to facilitate contact, an N + diffused layer in layer 9.

 FIG. 11 also shows a box 21 with junction insulation, the walls of which are formed by a deep diffusion of P-type silicon, 22, and in which a component can be implanted in a manner completely in accordance with bipolar technology. classic, for which the usual electrical insulation qualities are obtained with this technique. It is also possible to obtain boxes such as 23 resembling in all points to those obtained with the isoplanar technique already mentioned above When producing an integrated circuit on a silicon wafer according to FIG. 11 , the components which are likely to pose a particular problem of electrical insulation are preferably produced in boxes entirely insulated by silicon oxide, such as those which surround the transistors 14 and 15.

Claims (7)

CLAIMS: 1. A method of manufacturing bipolar integrated circuits with dielectric insulation comprising at least one box whose walls and bottom are formed by a layer of silicon oxide, said box resting on a substrate constituted by silicon and containing doped monocrystalline silicon of a first type of conduction in which a component is manufactured according to conventional bipolar technology, characterized by the following series of operations all carried out on the same previously polished face of the substrate - a monocrystalline silicon substrate of the second type of con  duction is locally oxidized, using LOCOS technology on a  zone delimited so as to constitute the bottom of said box; - an epitaxial layer of silicon is grown on the substrate  doped with the first type of conduction - we recrystallize the epitaxial layer. by  heating with sweeping - the walls of the said wall are produced using LOCOS technology  box. 2. A method of manufacturing bipolar integrated circuits according to claim 1 characterized in that the walls of said box are produced in two stages after the bottom of the box is made of silicon oxide - the first stage consists in growing on the substrate a  first thin epitaxial layer of doped silicon of the first type  conduction, to recrystallize the layer  epitaxially heated by sweeping and to be produced by  LOCOS technology the lower part of the walls of said cais  sound - the second step is to grow on the first layer  epitaxial a second epitaxial layer of pre doped silicon  mier type of conduction with a thickness between 0.11 and 0.95  times the depth of the box, and to be carried out using tech  LOCOS nology the upper part of the walls of said box. 3. A method of manufacturing bipolar integrated circuits according to claim 2 characterized in that it comprises, during the second step, the additional operation of practicing recrystallization of said second epitaxial layer of silicon by heating with scanning, just before operation, which consists of using the LOCOS technology to create the upper part of the walls of said box.  Method for manufacturing bipolar integrated circuits according to one of claims 1 to 3 characterized in that said first type of conduction is the donor type N, said second type of conduction being the acceptor type P. 5. A method of manufacturing bipolar integrated circuits according to claims 2 and 4 taken together or 3 and 4 taken together characterized in that said first epitaxial layer is of the heavily N + doped type. 6. A method of manufacturing bipolar integrated circuits aiming to produce at least one vertical PNP transistor inside said box according to claims 2 and 4 taken together or 3 and 11 taken together, characterized in that it comprises, between said first and second steps, the additional operation of creating by diffusion at the bottom of said box an area  P type, intended to become the emitter (respectively the collector) of said PNP transistor, the base of this transistor being constituted by a part of said second epitaxial layer of type N and the collector (respectively 11 emitter) by a diffusion restricted to the surface of said box in the second epitaxial layer, at least one other box for which deep P diffusion is not practiced being reserved for the production of a vertical NPN transistor. 7. A method of manufacturing bipolar integrated circuits according to one of claims 1 to 6 characterized in that it combines on the same integrated circuit wafer the bipolar technology with insulation by junction with the bipolar technology with dielectric insulation. 8. Bipolar integrated circuit obtained by implementing the method according to one of claims 1 to 7.