FR2543740A1 - Method of producing transistors by monolithic integration in isoplanar technology and integrated circuits thus obtained - Google Patents

Abstract

In order to ensure good electrical insulation, the method employs five adjacent layers of semiconductor material of alternately opposite type of conduction and includes the chronological succession of the following steps: a substrate 1 receives on a localised zone 2 impurities corresponding to a second type of conduction which is later surrounded by a guard ring 18; an epitaxial layer 4 is deposited; a thick oxide enclosure 5 is created on the said zone by LOCOS technology; a deep doping of the second highly doped type of conduction 6 which joins up with zone 2 is effected inside the enclosure; two nested dopings, base 7 followed by emitter 8, are effected inside the enclosure; the metal contacts of the electrodes 12, 13, 14 are established at the surface, the collector electrode 14 being at this time connected to the deep diffusion 6. Application: integrated circuits in isoplanar technology.

Description

METHOD FOR PRODUCING TRANSISTORS BY INTEGRATION
MONOLITHIC IN ISOPLANAR TECHNOLOGY AND INTEGRATED CIRCUITS SO OBTAINED.

The invention relates to a method for producing
sation of at least one transistor with vertical structure
PNP type and / or NPN type, by mono integration
lithic on a semiconductor material substrate
monocrystalline, using five adja layers
centes of semiconductor material of conduc type
opposite alternation among which the subs
trat is counted as the first layer, according to which
a metallization connects the second and third
layers. The invention also relates to circuits
integrated obtained by the implementation of this process.

We know monolithic structures
comprising so-called vertical type transistors
NPN and / or PNP type, developed on the same substrate
P or N type, each with a region
insulating material opposite to that of the substrate. We can
see for example on this subject in the book
"Handbook of Semiconductor Electronics", by
LLOYD P. HUNTER, third edition, Mc-GRAW HILL BOOK
Company. In Figure 5-6 (b), page 5-10, we find the
representation of a structure with a transis
tor PNP and an NPN transistor developed on a substrate
of type N, the corresponding explanations being
provided on page 5-11.

In this known structure, a transistor
PNP type produced for example on a substrate of
type N, comprises from the substrate, a layer of
deepest type P of the transistor, which constitutes
the collector of the transistor and which constitutes at the same
time the insulating region, an N-type layer and a P-type layer which respectively constitute the base and the emitter of the transistor. An NPN type transistor produced on a substrate of the same N type has an additional layer, that is to say from the substrate, a P type layer which constitutes the insulating region, a deepest N type layer of the transistor, which constitutes the collector of the transistor, finally a P-type layer and an N-type layer which respectively constitute the base and the emitter of the transistor.

 As the author of the aforementioned book notes at the end of paragraph 5-2c, in such a structure, parasitic transistors and four-layer circuits with switch function are formed under certain polarization conditions. This can result in leakage currents from the useful transistors to the substrate, and therefore an insulation fault between these transistors, which limits the use of this technique.

The object of the present invention is to produce NPN or PNP vertical transistors, the electrical insulation of which is improved compared to that of transistors produced in conventional bipolar technology.
Another object # of the invention is to produce complementary NPN and PNP transistors with junction isolation, the electrical insulation of which is improved compared to that of the complementary transistors produced in conventional bipolar technology.

We know from the French patent application registered under the number 82 w5 879 in the name of the plaintiff ', a process for producing transistor (s) with vertical structure by monolithic integration on a substrate of semiconductor material, according to which - each transistor is obtained by insertion (diffu
ion implantation) in a substrate of
conductivity type P or N, of a built-up box
killed layers of con semiconductor material
alternate ductivities, the number n of which is at least
equal to two, the farthest layer of the box
of the substrate constituting the collector layer of the
transistor from which are installed the
base layers, then emitter - among these n layers, there is at least one neck
full of two adjacent layers between which
a low value resistance is developed or
almost zero, consecutive couples using
different layers.

 The fact of electrically connecting two of the adjacent layers of the box, included between the substrate and the base of the transistor and whose conduction types are opposite, amounts to short-circuiting the base and the emitter of a parasitic transistor exists both between the useful transistor and the substrate, that is to say to inhibit the operation of this parasitic transistor and therefore to prevent any leakage current towards the substrate, and this whatever the potentials applied on the electrodes of the useful transistor, in particular in the if the latter is saturated.

The present invention aims to implement the electrical property described in the previous paragraph in the simplest case where only two layers are interposed between the substrate and the base of the transistor, by proposing a precise technical implementation. To this end, the present invention is remarkable in that the process defined in the preamble implements iso planar technology and comprises at least the chronological succession of the following stages - Said substrate of a first type of conduction re
çoit on an area provided for the location of said
impurity transistor corresponding to the second
type of conduction - A guard ring is introduced from place to place - The single crystal is grown by making a
monocrystalline deposit of the first type of conduction - We operate by means of LOCOS technology an oxy
deep dation which joins the edge of said area
so as to constitute an enclosure - One carries out inside said enclosure a do
deep page of the second type of strong conduction
doped which joins said zone - It is carried out inside said enclosure, sep
said deep doping, two nested dopings
base then transmitter - The metal contacts constituting the electrodes
of said transistor are established on the surface, the electro-
of collector being, on this occasion, connected
deep doping audit.

 By proceeding in this way, the lateral electrical insulation of the transistor, in particular the suppression of lateral leakage currents is ensured by thick oxide walls and the suppression of vertical leakage currents is ensured by a short circuit established between the two adjacent layers of the box, one of which is the collector of the transistor and the other an insulation layer interposed between the collector and the substrate.

 According to a first embodiment of the invention, there is created, inside said enclosure, a silicon chimney with oxide walls inside which said deep doping is carried out.

 According to a second embodiment of the invention, there is created, by etching inside said enclosure, a well of depth substantially half that of the enclosure at the bottom of which is carried out at the same time as the basic doping said deep doping then, at the same time as the emitter doping and adjacent to said deep doping, the collector socket heavily doped with the first type of conduction.

 According to an embodiment compatible with the previous ones, the method according to the invention is remarkable in that, in addition to said transistor, at least one second transistor complementary to said transistor is produced on said substrate inside a second enclosure constructed from the same way as said enclosure, the emitter of which is constituted by said zone of the second type of conduction relative to the second enclosure, the base by the layer of the first type of conduction which constitutes the interior of said second enclosure and the collector by a layer of the second type of conduction created in said base.

 The following description with reference to the accompanying drawings, all given by way of example, will make it clear how the invention can be implemented.

 FIG. I represents in section in a, b, c, d, e and f, 6 successive stages for the implementation of the method according to the invention.

 Figures 2a and 2b show in section a first preferred embodiment of the invention.

 Figures 3a and 3b show in section a second preferred embodiment of the invention.

 Figure 4 shows in section an embodiment of the invention compatible with the previous ones.

 In the different figures, the same references designate the same elements with the same functions.

 Figure la represents a piece of substrate l of a first type of conduction shown in white, which can be type N (donor) or type P (acceptor). To fix the ideas, it is assumed in the rest of the text that the first type of conduction is type N, the second type of conduction, opposite to the first and represented by spaced hatching being then type P. We propose to elaborate on this piece of substrate a transistor with vertical structure by monolithic integration, by implementing five layers of semiconductor material of alternating type of conduction in alternation and by carrying out at most two nested dopings. Under these conditions, the substrate is of type P for a PNP transistor or of type N for an NPN transistor. The second case is chosen here by way of example. The substrate l being a monocrystalline wafer of type N (or N -), local impurities by type P are brought locally by conventional means, for example by diffusion, into a surface zone 2 intended to become the bottom of a box of isolation. This contribution of trivalent impurities can consist of ion implantation or diffusion; the masking (first mask) is done by photosensitive lacquer; in the case where the process uses diffusion, the masking must resist a high temperature and it generally consists of oxide. The next step is to create zones 18 located around zone 2, a short distance from the latter but without contact with it. It is a cord of the first type of highly doped conduction (N + in this case ), intended to attenuate the effect of a parasitic MOS transistor which can be established at this level, by increasing the threshold voltage of the latter.

As described below, thick oxide layers are created, in a subsequent step, above the cord 18. These oxides, intended to separate the transistor from other elements are thus protected by guard rings constituted by the cord 18 not in contact with zone 2 and which may be discontinuous, being only present from place to place, which in particular allows better resistance to tension.

 An optional step, reserved for the realization of an NPN transistor is possible. This involves creating a heavily doped N area 3, housed inside the area (s) P, 2. A second mask is used for this purpose; this mask must be positioned inside the openings of the first mask, so that in any case the N + layer cannot come into contact with the type 1 substrate 1. The zone 3 can hard deposited at the same time as the ring guard 18, using the same second mask.

 The next step, FIG. 1b, consists in growing the crystal by proceeding with a silicon monocrystalline 4 of the first type of conduction (type N), this operation being entirely conventional in the production of integrated circuits. This operation being carried out on the whole of the surface of the silicon wafer (or wafer) does not prevent the use of a specific mask. The doping 'of this layer as well as its thickness are variable and greatly depend on the performance in tension expected on the finished product.

 An important characteristic of the invention consists, in combination with the establishment of zone 2, in producing around the future transistor a chamber made of thick silicon oxide which joins the edges of zone 2 and which is referenced 5, FIG. lc et seq., which amounts to implementing isoplanar technology which is moreover known per se, to ensure good lateral electrical insulation and thus avoid any lateral leakage current towards the substrate. To obtain this high oxide thickness which must be slightly greater than that of the epitaxial layer 4, the technique known by the name of LOCOS, preferably used by the French company R.T.C., is preferably used. and more generally by the Dutch company PHILIPS, especially for the production of MOS structures. This technique consists in first depositing a thin layer of nitride, Si3N4 on the entire wafer; this thin layer is then photograved with precision at the locations chosen for the diffusions; it is then possible to grow thick layers of Si4 on on the silicon thus exposed and to remove the residual layers of nitride. Improvements have been made to the LOCOS technique indicated above: to obtain better adhesion of the nitride layer, provision may be made to cover the substrate, before deposition of the nitride, with a very thin layer of silica. On the other hand, the generation of thick silicon oxide causes swelling of the oxidized zone. To obtain good final flatness of the treated surface, one means consists, after stripping of the nitride layer at the places to be oxidized and before oxidation, to etch the silicon at these locations to a depth equivalent to 10 to 20% of the thickness of the oxide layer to be created. The LOCOS technique is made possible by the fact that there are selective strippers, some attacking the nitride and not the oxide, others, on the contrary, attacking the oxide without attacking the nitride. Oxidation is generally done in high temperature ovens at different speeds depending on the process used. Dry heating with oxygen can be used or operating in the wet phase, in the presence of water vapor. The enclosure 5 is produced by means of a third mask. It will be noted that it may be advantageous to carry out the successive epitaxy-oxidation stages in two stages, even if it means using the third mask twice. In fact, the LOCOS process makes it possible to obtain thick layers of silica. However, the oxidation speed decreases with the depth to be reached and it can be long and therefore expensive to obtain thicknesses of the order of 10 μm for the production # of the enclosure. The fact of repeating the operation by treating each time only about half of the final thickness desired for the layer 4 therefore overcomes this drawback. We will see below that this method of der is essential for the second embodiment of the invention.

 Figure id presents the next step which consists, by means of a fourth mask, in carrying out inside the enclosure 5 a deep doping of the second type of conduction (P or preferably P +, in this case said DP or DP +), by diffusion or by ion implantation. This creates a zone 6 which joins the buried zone 2 at a location separate from zone 3, so as to create contact with zone 2, brought to the surface. This step constitutes an additional phase in the localized oxide system (isoplanar).

Therefore, as shown in Figures le and if, the process becomes entirely conventional and conforms to conventional bipolar technology. At least two diffusions (or ion implantations) are still necessary for the realization of the transistor inside the enclosure: a basic P doping creating the zone 7 by means of a fifth mask, and a doping
N (or preferably. N +) of transmitter which creates a zone 8 of transmitter inside zone 7 and a zone 9, separated from zones 7 and 8 for making contact with the collector, all by means of 'a sixth mask. Then the metal contacts are made up constituting the electrodes of the transistor, which require a seventh and an eighth mask for the opening of the contacts, and a ninth mask of engraving of aluminum. One thus obtains the NPN transistor of the figure if, covered with 'a thick layer of silicon oxide il through which are made the emitter 12 base 13 and collector 14 contacts, the metal parts (preferably aluminum) being represented by tight hatching. Sectors using technique
LOCOS often have, not shown, two interconnection layers, using two additional masks. In addition, it may be advantageous to produce a collecting well connecting the collecting socket 9 to the buried layer N +, 3, which requires an additional mask. This last operation, not shown, takes place before the basic and transmitter broadcasts.

 The transistor thus obtained, called useful transistor, implements, in the vertical direction five layers of alternating conductivities which are from top to bottom in the figure if the emitter, the base, a box consisting on the one hand of the essential of the epitaxial layer N situated in the enclosure 5 which constitutes the collector 15, and by the layers 3 and 9, on the other hand by the layer 2, and a fifth layer constituted by the substrate 1.

In known structures of vertical bipolar transistors with insulating region, the N-type collector layer is implanted directly on a P-type substrate and there is the aforementioned drawback of leakage currents to the substrate, under certain polarization conditions. of the useful transistor, in particular those which bring it to saturation, due to the parasitic transistor which the substrate can form with the layers 15 and 7. To overcome this drawback, the French patent application number 82 15 879 already cited teaches that can first of all fashion for the useful transistor a box constituted by n alternating conductivity layers n being greater than or equal to 2. This is indeed the case in the figure if where the two layers of the box are referenced 2 and 15; then, to obtain the desired insulation, constitute among the n layers of the box at least a pair of two adjacent layers between which is developed a resistance of low or almost zero value intended to practically short-circuit these two layers. In the case of the present invention, it is therefore a question of short-circuiting the layers 2 and 15, which is done, in the figure
If by means of the conductor 14 which is connected both to the N layer, 15, by the N + zone, 9, and to the layer 2 by the P + zone, 6. If the electronic diagram of the assembly is made constituted by FIG. If, one obtains essentially, in addition to the useful transistor NPN 8,7,15 a first parasitic transistor PNP 7,15,2 and, arranged in series with the useful transistor, a second parasitic transistor NPN 15,2, 1, the substrate 1 of which constitutes the collector. By short-circuiting the base 2 and the emitter 15 of this second parasitic transistor, any transistor effect is eliminated and the emitter-collector current of this second parasitic transistor is thus reduced to a negligible value, which is identified with a current of leakage to the substrate.

 It is clear that a PNP transistor can be produced in a similar manner protected against lateral and / or vertical leakage currents to the substrate, by replacing, in FIG. 1, the N or N + zones by P or P + zones and vice versa. . In this case, however, the optional step of creating layer 3 is omitted. In practice, the development of doping 6 described above with reference to FIG. 1d can lead to drawbacks and in particular require too much space inside the array 5. To reduce these drawbacks, two preferred embodiments are described below with reference to Figures 2 and 3 respectively.

 In FIG. 2a, a silicon chimney with thick oxide walls is created over the entire thickness of the epitaxial layer 4. To do this, a partition 16 in thick oxide is added to the enclosure 5, the lateral ends of the partition 16 being in contact with the enclosure 5. The partition 16 is produced by means of the same mask which is used for the enclosure 5 and its lower part thus comes into contact with the deep layer 2. Deep doping 17 of the second type conduction is then carried out by means of the fourth mask, inside the chimney of any shape, for example rectangular thus created between the wall 16 and the enclosure 5, which exactly delimits the part to be doped and which prevents extension by unwanted diffusion of this part during subsequent heat treatments of the integrated circuit board. It will be noted, in FIG. 2a as well as in the following figures, the presence of the zones 18 situated just below the enclosure 5 which constitute a guard ring. This guard ring can be removed as described above with reference to Figure la. It is also possible, after deposition of the epitaxial layer 4, to produce, using a specific mask, N + doping in the form of a closed bead at the location of the future enclosure. During the subsequent preparation of the enclosure 5, this N + cord is then repelled by the oxide and migrates towards the substrate until it occupies the location shown in FIGS. 2, 3 and 4. The following operations, which makes it possible to pass from FIG. 2a to FIG. 2b representing the complete transistor with its contacts is # the same as that which makes it possible to pass from FIG. 1a to FIG. If.

 FIG. 3 represents a second preferred embodiment of the invention, according to which the joint contacting of the layers 2 and 15 takes place in a depression or well created by removal of silicon in the layer 15 located inside the 'enclosure 5. Figure 3a highlights the first steps necessary for the formation of this well.

The deposition of the epitaxial layer and the constitution of the enclosure are carried out here in two stages. First, an N, 21 layer is cut by epitaxy, the thickness of which is substantially half the epitaxial layer necessary for the die. This operation being carried out on the whole of the silicon wafer, does not require a mask. Then, in accordance with LOCOS technology, the layer 21 is covered with a thin oxide layer allowing the bonding and then subjected to a deposit of silicon nitride Si N. The lower parts of the enclosure are formed as described above with reference to FIG. 1c (third mask). The remaining layer of silicon nitride is then removed by pickling except for one location (fourth mask ) which corresponds substantially to that of the chimney for the first preferred embodiment (Figure 2). A pellet of Si3N4, 23 is thus obtained located substantially against the enclosure directly above the part of the insulation layer 2 which does not include the buried layer 3. A second epitaxial layer N is then deposited on the whole surface so as to obtain the total thickness desired for the epitaxial layer. The resistivity of this layer 24 can be the same or different from that of the underlying layer 21. If this deposit is made with the required care, it can be entirely monocrystalline. However, above the lower part 22 of the enclosure and the pellet 23, many defects can exist in the crystal lattice and it can even happen that we have polycrystalline silicon. However, as will be seen below, use will not be made of the silicon deposited above the nitride 23 or of the silica 22 to conduct the electricity and therefore the nature of the deposited silicon does not have a very large importance. During the growth of the single crystal, the twins will tend to extend obliquely to a line perpendicular to the surface of the wafer and it may be necessary to take this into account in determining the minimum dimensions of the enclosure. .Moreover, in the case where crystalline faults would cause the efficiency of the useful transistor to drop too low, methods exist, described elsewhere, based on annealing or localized fusions in particular, so as to make it possible to reduce the number of these faults, such as for example the process described in the publication "Electronics Review" of June 2, 1982, pages 45 and 46 in two articles, one by J. Robert LINEBACK, the other by Roderic BERESFORD.

The next step consists in producing the upper part 25 of the enclosure (fifth mask), still using LOCOS technology, which makes it possible to obtain a structure substantially identical to that of FIG. 1c with, in addition, the presence of the silicon nitride pellet 23 at mid-thickness of the epitaxial layer inside the enclosure.

It will be noted that the third and fifth masks are practically identical. Using a sixth mask, the nitride is removed by pickling where it is desired to etch the silicon, that is to say above the wafer 23. The nitride remaining on the surface is referenced 26, FIG. 3a. Then, using a selective stripper, a chemical etching is carried out which attacks the silicon alone, with the exclusion of silica 25 and nitride 26. This etching is stopped in depth by the nitride pellet 23.

The layers 23 and 26 are then completely removed by pickling and the entire surface # of the wafer is oxidized, these last two operations not being shown. Using a seventh mask, the surface oxide is opened to carry out the basic doping (P or P +) 27, FIG. 3b and, simultaneously, that is to say using the same mask, at l location of the part of the old pellet 23 situated on the enclosure side, the surface oxide is opened to carry out the deep doping 28 intended for contacting the zone 2. In this case, this doping 28 has the same thickness as that of the base 27, this thickness being necessarily greater than that of the epitaxial layer 21. In an analogous manner, the emitter is then doped, by an eighth mask, which results # e in an N + d zone emitter 29 inside the zone 27 and in a zone N of collector socket, 31, adjacent to the #one 28 and whose thickness is less than that of the layer 21. The emitter contact sockets 32 , base 33 and manifold 34 are then made and, on this occasion, it may be necessary to use more than two masks for the drilling of the surface layer of silica 35, with the aim of making stepped openings intended to avoid subsequent breakage of the aluminum which will then be deposited in these openings. The constitution of steps is particularly recommended to make the collector contact 34 which is the deepest and therefore the most exposed to breakage.

 The metallic contact common to layers 2 and 15, 34 is here achieved simply through a single drilling of the surface oxide layer since the contacting areas of these two layers, 28 and 31 respectively, are adjacent. The simultaneous creation of dopings of silicon a few microns apart from each other in the vertical direction, that is to say on non-strictly flat surfaces (zones 27 and 28 or 29 and 31) can pose some technological difficulties relating to the sharpness of the image formed on the wafer. However, a person skilled in the art has several methods for insulating the wafer through the mask and can easily resolve these difficulties by taking advantage of the tolerances allowed by each of these methods.

 In addition, in the case of the desired sharpness for the formation of the zones 28 and 31 would not be optimal; it is always possible to enlarge the area of the patch 23 and thus increase the lateral space tolerances even if it means slightly enlarging the enclosure of the transistor.

In FIG. 4 are shown two complementary transistors, at the rate of a vertical NPN transistor 36 on the right part of the figure and of a vertical PNP transistor 37 on the left part of the figure. For transistor 36, the representation of FIG. If has been chosen, but it may also be the transistor according to FIG. 2b or the transistor according to FIG. 3b. To make the transistor 37, the first steps are identical to those described above with reference to Figures la to ld, except that the layer 3 does not exist in this case. Then a type area
P 38 analogous to zone 7 is implanted (diffused) in layer 4. Zone 38 will be the emitter, respectively the collector of transistor 37, zone 39, analogous to deep zone 2 and developed using the same mask will be the collector, respectively the emitter, and the N type intermediate zone, 41, the base of the transistor 37. The contact sockets 42, 43, 44 of the zones 38, 41 and 39 are produced as in the figures if or 2b for the NPN transistor but in this case, there is no common contact between two adjacent layers of types of opposite conduction, each of the three electrodes 42, 43 and 44 being connected to only one of the zones 38, 41, 39. We note that the P 45 doping for making contact with the layer 39 can also be carried out as described above in 17 with reference to FIG. 2. One thus obtains a vertical PNP transistor 37 whose performance is less good than that of the NPN 369 transistor but better than those of a lateral PNP transistor c as is commonly done in isoplanar technology or as those of a vertical PNP transistor in a conventional integrated circuit with four layers for which the substrate itself acts as emitter or collector, which implies the existence of a substrate current and setting the same potential - that of the substrate - of homologous electrodes of all the PNP transistors thus produced on a common substrate.

 The present invention proposes to produce complementary transistors while avoiding any leakage current to the substrate. It will be noted that the transistor 37 of FIG. 4 could cause a leakage current to the substrate under certain particular conditions of polarization of its electrodes, that is to say if its emitter was constituted by the zone 38 and if it was brought to saturation, which would result in the unblocking of the parasitic NPN transistor which exists between the useful transistor PNP and the substrate. To avoid this, the transistors such as 37 are polarized so that the area 39 constitutes the emitter, the area 38 then being the collector.

In addition, the diagrams of the electronic circuits to be produced by integrated circuits which require additional transistors can be designed in such a way that there is only one type of transistors, preferably NPN transistors, which is capable of being brought to saturation. When the NPN transistors are produced according to the invention as described above with reference to Figures if, 2b or 3b, it is then ensured that they cannot be the cause of a leakage current to the substrate. In order to further reduce any risk of substrate current, a specific connection of the circuits must be made: the N-type substrate must be connected to the most positive point of the circuit, that is to say in general to the voltage of most positive power supply on the circuit.

 It goes without saying that between the transistors produced as described above it is possible to obtain any desired integrated circuit to produce at the same time on the same silicon wafer other components such as diodes or resistors for example, of the same so that in isoplanar technology or, more generally in conventional bipolar technology. Furthermore, the preferred embodiments of the invention have been described above with reference to FIGS. 1 to 4. It will be noted in this regard that it is also possible to produce integrated circuits in accordance with the invention by reversing the types of doping indicated for FIGS. 1 to 4, that is to say by replacing the type regions N by P-type regions and vice versa.

Claims (6)

CLAIMS: 1. Method for producing at least one transistor with a vertical structure of PNP type and / or of NPN type, by monolithic integratinn on a substrate of monocrystalline semiconductor material, using five adjacent layers of semiconductor material of opposite conduction type in alternation among which the substrate is counted as the first layer, according to which a metallization connects the second and third layers, characterized in that it implements isoplanar technology and comprises at least the chronological succession of the following stages - said substrate of a first type of conduction re  believes in an area provided for the location of said  impurity transistor corresponding to the second  type of conduction - a guard ring is introduced from place to place - the single crystal is grown by making a  monocrystalline deposit of the first type of conduction - we operate by means of LOCOS technology an oxy  deep dation which joins the edge of said area  so as - to constitute an enclosure - one carries out inside said enclosure a  deep doping of the second type of conduction  heavily doped which joins said zone - it is carried out inside said enclosure, separa  said deep doping, two nested dopings  base then transmitter - the metal contacts constituting the electrodes  of said transistor are established on the surface, the  collector trode being, on this occasion, connected  deep doping audit. 2. A method of making transistor (s) with vertical structure according to claim 1, characterized in that said semiconductor material is silicon and that said first type of conduction is type of N conduction. 3. A method of making transistor (s) with vertical structure according to claim 1 or 2 characterized in that there is created inside said enclosure a silicon chimney with oxide walls inside which is performed said deep doping. 4. A method of making transistor (s) with vertical structure according to claim 1 or 2 characterized in that it is created by etching inside said enclosure a well of depth substantially half that of the enclosure at the bottom which is carried out at the same time as the basic doping said deep doping then at the same time as the emitter doping and adjacent to said deep doping, the collector socket heavily doped with the first type of conduction.  5. A method of making transistor (s) with vertical structure according to one of claims 1 to 4 characterized in that there is developed on said substrate at least one second transistor complementary to said transistor inside a second built enclosure in the same way as said enclosure, the emitter of which is constituted by said zone of the second type of conduction relating to the second enclosure, the base by the layer, of the first type of conduction which constitutes the interior of said second enclosure and the collector by a layer of the second type of conduction created in said base. 6. Integrated circuit in isoplanar technology obtained by the implementation of the method according to one of claims 1 to 5.