FR2535527B1 - METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT - Google Patents

METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT

Info

Publication number
FR2535527B1
FR2535527B1 FR8218240A FR8218240A FR2535527B1 FR 2535527 B1 FR2535527 B1 FR 2535527B1 FR 8218240 A FR8218240 A FR 8218240A FR 8218240 A FR8218240 A FR 8218240A FR 2535527 B1 FR2535527 B1 FR 2535527B1
Authority
FR
France
Prior art keywords
insulating layer
integrated circuits
corresponding circuit
manufacturing silicon
silicon integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8218240A
Other languages
French (fr)
Other versions
FR2535527A1 (en
Inventor
Jean-Pierre Brevignon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8218240A priority Critical patent/FR2535527B1/en
Publication of FR2535527A1 publication Critical patent/FR2535527A1/en
Application granted granted Critical
Publication of FR2535527B1 publication Critical patent/FR2535527B1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
FR8218240A 1982-10-29 1982-10-29 METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT Expired FR2535527B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8218240A FR2535527B1 (en) 1982-10-29 1982-10-29 METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8218240A FR2535527B1 (en) 1982-10-29 1982-10-29 METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT

Publications (2)

Publication Number Publication Date
FR2535527A1 FR2535527A1 (en) 1984-05-04
FR2535527B1 true FR2535527B1 (en) 1986-05-16

Family

ID=9278771

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8218240A Expired FR2535527B1 (en) 1982-10-29 1982-10-29 METHOD FOR MANUFACTURING SILICON INTEGRATED CIRCUITS COMPRISING CLOSED ELECTRODES ON AN INSULATING LAYER AND CORRESPONDING CIRCUIT

Country Status (1)

Country Link
FR (1) FR2535527B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2679379B1 (en) * 1991-07-16 1997-04-25 Thomson Composants Militaires METHOD FOR MANUFACTURING INTEGRATED CIRCUITS WITH VERY NARROW ELECTRODES.

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
DE2939456A1 (en) * 1979-09-28 1981-04-16 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING INTEGRATED SEMICONDUCTOR CIRCUITS, IN PARTICULAR CCD CIRCUITS, WITH SELF-ADJUSTED, NON-OVERLAPPING POLY-SILICON ELECTRODES
JPS56135975A (en) * 1980-03-27 1981-10-23 Seiko Instr & Electronics Ltd Manufacture of semiconductor device
JPS56137657A (en) * 1980-03-29 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Also Published As

Publication number Publication date
FR2535527A1 (en) 1984-05-04

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