FR2527878A1 - SIGNAL PROCESSING CIRCUIT FOR TELEVISION CAMERA WITH MATRIX IMAGE DETECTOR AFFECTING LOCALIZED FAULTS - Google Patents

Abstract

THE INVENTION RELATES TO MATRIX-TYPE ANALYZER TELEVISION CAMERAS. TO ELIMINATE LOCALIZED PERMANENT FAULTS OF THE ANALYZER, THE SIGNAL EMITTED BY THE PREVIOUS POINT IS USED IN THE PLACE OF A FAULTY POINT. DEFECTIVE POINT ADDRESSES ARE STORED IN A PROGRAMMABLE DEAD MEMORY 10, AS ARE THE ADDRESSES OF FULL COLUMNS OF DEFECTIVE POINTS (WITHOUT STORING ALL THE POINTS OF THIS COLUMN). AT EACH IMAGE, THESE COLUMN ADDRESSES ARE TRANSFERRED INTO A VOLATILE RAM 30 MEMORY. A CORRECTION ORDER IS SENT: - EITHER WHEN YOU GO (COMPARATORS 22 AND 24) TO A FAULTY POINT (STORED IN PROM MEMORY); THE PROM MEMORY IS THEN INCREMENTED TO INDICATE THE NEXT FAULTY POINT, AND IT IS RESET AT THE END OF THE IMAGE SCAN; - EITHER WHEN GOING (COMPARATOR 38) OVER A FAULTY COLUMN (CONTAINED IN THE RAM MEMORY); THE RAM MEMORY IS THEN INCREMENTED TO INDICATE THE NEXT FAULTY COLUMN AND IT IS RESET AT THE END OF EACH LINE SCAN.

Description

SIGNAL PROCESSING CIRCUIT FOR TELEVISION CAMERA A

  MATRIX IMAGE DETECTOR AFFECTING LOCALIZED FAULTS

  The present invention relates to image matrix detector television cameras, for example those which operate with a solid-state image analyzer with data transfer registers.

loads (called CCD registers).

  This type of detector is difficult to manufacture because of the very great pattern of the circuit elements that constitute them, and it often happens that points, or even lines or entire columns of points of the detector, are defective and translate, when rendering on a screen an image filmed by the camera, by points, or lines or

  columns of black or glittering fixed points unpleasant to the eye.

  If we do not want to dispose of the solid analyzer when it has one or more localized defects, we can overcome these defects by processing the signal from the analyzer, for example by replacing the signal from a point defective by the signal from the (non-defective) point which precedes it, or by the average of the signals corresponding to the point

previous and next point.

  For this, we find, for a given analyzer, the exact location of each of the defective points; as the

  image detector is of the matrix type, the photosensitive elements

  are branched into a network of rows and columns, and each defective item can be spotted by a line address and

a column address.

  These addresses are stored in a non-memory

  volatile, at successive positions, in order of points

  defects encountered during the exploration of the surface area

  tosensible; to each analyzer, therefore to each camera will correspond a programmable non-volatile memory (PROM memory) containing the

  addresses specific defective points of this camera.

  During camera operation, the image projected on the analyzer is scanned line by line, and point by point on each line; PROM memory initially provides the address

  the first defective point; this address is compared in

  manence at the address of the current point explored, that is to say the point treated at a given instant by the signal processing circuit of the camera; if there is coincidence, a correction command is sent and the memory is commanded to then supply the address of the next defective point; for this, the addressing of the memory is incremented which brings it to the next memory position; this incrementation is renewed each time a defective point is met, until the end of the exploration of the image The memory is reset to its

  first memory position with each new image scan.

  The disadvantage of this type of treatment is that if a

  entire column of points is defective, it can not be

  try to write in the memory a global address of column

  each point of this column must be entered individually.

  Indeed, the signal due to the defective points can only be corrected point by point as the exploration and not for a group of points in column because the

  Column points do not follow each other in the exploration of the image.

  So you can not jump from one point of the column to a next point in the same column without having first examined the other defective points in the order of the exploration that is done online.

by line.

  However, if the analyzer comprises for example 500 rows and 500 columns (250 000 elements), each point address is broken down for example into a word of 10 bits of line address and

  a 10-bit word of column address.

  If 20 isolated points are defective, 20 addresses of 20 bits (400 bits) will have to be memorized; if two more columns are defective, it will not be two column addresses (2 x 10 bits) which will have to be stored in the PROM memory but 2 times 500 addresses of points (2 x 500 x 20 bits) or about 20 000 bits A total of 20 400 bits will have to be stored in programmable memory for 20 defective isolated points and 2 defective columns. The memory capacity will have to be very

  high when a column is defective.

  The present invention provides an improved processing circuit that eliminates this disadvantage by enabling the addresses of entire faulty columns to be stored in the programmable memory without registering the row and column addresses.

from all points of these columns.

  For this, we add to the non-programmable memory

  volatile (PROM), a volatile memory (RAM) and issuing orders

  defect correction either from the PROM memory which

  holds the addresses of faulty isolated points and which is explored

  cyclically to each image, its addressing being incremented every

  passing through a defective point, either from the RAM which contains the addresses of entire columns defective and which is cyclically explored at each line, its addressing being incremented each time a column is defective The addresses of entire columns defective are listed in the PROM memory and are transferred to the RAM memory at the time of

  under power or repeatedly at the beginning of each image.

  Cyclic line-by-line scanning of RAM makes it unnecessary to record in this memory (and

  therefore in the PROM memory where they are drawn) other information

  than the addresses of defective columns (10 bits per

defective column).

  Thus, not only can the PROM memory be reduced practically to the capacity necessary to record the addresses of faulty isolated points, but it is not necessary to provide a second PROM memory for

  the separate recording of the addresses of defective columns.

  The circuit according to the invention comprises for this purpose a non-volatile programmable memory; a first comparator for comparing the contents of the memory to an explored current-point address and providing a

  control signal of correction in case of coincidence of this con-

  held and this address; a volatile memory coupled to the nonvolatile memory for storing whole bad column addresses contained in the nonvolatile memory; a second comparator for comparing the contents of the volatile memory with a current column address corresponding to an explored point, for providing a correction control signal if there is coincidence between that content and that address; a control circuit of the volatile memory to increment the addressing thereof after each coincidence detected by the second comparator, to reset this addressing to each searched line, and to initially perform the recording in the memory volatile

  addresses of entire columns defective.

  The initial transfer of the PROM memory into the RAM memory can be done during the frame returns, after the end of an image scan and before the beginning of the next scan; a sequencer then performs a systematic transfer of the addresses of entire columns defective (identified as such for example by a specific bit) or a transfer of an entire area of the PROM reserved for storing the column addresses

defective whole.

  The transfer can also be done during the exploration of the first line: among the defective points of the first line, some will be isolls; others, marked for example by a specific bit will correspond to-addresses of entire columns defective that will be recorded in the RAM for the correction of these columns from the RAM and not the PROM during the scanning of the

following lines.

  Other features and advantages of the invention

  appear on the following detailed description

  and which is made with reference to the accompanying drawing which represents a

  schema of the correction control circuit according to the invention.

  The addresses of defective points are written in a programmable nonvolatile memory (PROM). This PROM 10 is controlled by a control circuit 12 which notably makes it possible to increment or reset an address counter 14 of the memory. 14 indicates successively

  the addresses of the PROM memory that one wishes to read.

  in the following not to confuse the addresses of the PROM memory 10 and the addresses of defective points or columns

  defective which are contained at these addresses of the memory 10.

  During the scanning of the image, the counter designates at a given moment a memory address PROM 10 A this

  address is contained the designation of the next defective point.

  It is therefore this designation, for example 10 bits of line address and 10 bits of column address which appears at the output of the memory 10 and which can be registered in an address register.

  line 16 and a column address register 18.

  It will be assumed that the words are eleven-bit words (10 bits of line or column address and possibly an eleventh bit whose usefulness will be specified). ; two successive words are read at each incrementation of the counter 14, the first word (line address) being placed in the register 16 and the second (column address) in the register 18, thanks to a demultiplexing circuit 20 controlled by the circuit The words could be eight-bit words while 10 bits are needed for coding a row or column, in which case three words per bad point would have to be read, the demultiplexing circuit

being a little more complex.

  The addresses contained in the registers 16 and 18 are continuously compared in respective comparators 22 and 24 at the current address (in line and column) of the point explored.

  to say of the point being processed by the processing circuit.

  This signal is easily obtained from the processing circuit.

  signal that this analyzer is of matrix type.

  When there is coincidence between the address of the defective point provided at a given moment by the memory 10 and the address

  the current point explores, ie when both

  22 and 24 simultaneously provide a coincidence signal to an AND gate 26, a correction control command is transmitted to the output of this gate and, through an OR gate 28, to the output S of the circuit of FIG. rest of the circuit

  signal processor (not shown) that performs the correction

  necessary (replacement of the signal corresponding to this defective point by the signal from the preceding point or the average of the preceding point and the next point) The presence of a coincidence signal at the output of the AND gate 26 at the same time controls the incrementation the counter 14, through the control circuit 12 to put in the registers 16 and 18 the address of the next defective point, and so on until the end of the scanning of the image A frequency signal Fi resets counter 14 to restore, for scanning

  next, the position of the first defective point of the image.

  According to the invention, the PROM 10 memory contains essentially

  only the addresses of isolated defective points If an entire column is defective, only the address of this column (or the first point of this column), and not the addresses of all the points of the column, will be recorded in the PROM, in the form of a 10-bit address and possibly an eleventh bit indicating that it is a column address

whole faulty.

  A volatile memory (RAM 30) is connected to the output of the register 18 to record the addresses of entire defective columns, identified either by the eleventh bit, or by their

  storage in a particular area of the PROM memory 10.

  A counter 32 controls the addressing of the RAM memory, either for writing or for reading, and a control circuit 34 controls the incrementation and reset of this memory.

  counter, as well as the read / write mode of the RAM 30.

  A sequencer 36 controls the control circuits 12 and 34 of the memory 10 and the memory 30 to define read times

  or writing during circuit operation.

  On power-up, or better still at the beginning or before the beginning of each image scan, the sequencer defines a transfer period, to the volatile memory 30, of the addresses of whole columns defective contained in the

non-volatile memory 10.

  For example, the sequencer can receive, during a frame return, a signal at an image frequency Fi to trigger a write period of the RAM memory. During this period, all the addresses contained in a certain area of the ROM memory are transferred to RAM memory; or then, all

  column addresses identified by their eleventh bit (whose posi-

  The transfer is carried out at a frequency f as high as possible taking into account the possibilities of the memories 10 and 30 (for example a frequency f = 1.1 M Hz, the counters 14 and 32 are incremented at this frequency during the transfer). In another sequencing possibility, this transfer does not take place during the frame return but during the first line of analysis of the image: in this case, the address of a defective column is stored in ROM memory. the place where the address of the first defective point of this column would have been stored if all the defective points were considered as isolated points The other points of the entire defective columns are not stored in memory, and the first point of a whole column the 11th bit being transmitted from the register 18 to the control circuit 34 of the RAM memory via a connection 19 during the first line of analysis of the memory. image, there will be encountered successively in the memory 10 a defective isolated point address, then a point of a defective integer column; this point, identified as such by its eleventh bit in the register 18, forces the writing in the RAM 30 of the address of the corresponding column, at the same time that a correction command is given by the coincidence signals in output of the comparators 22 and 24, and at the same time as the addressing of the two memories, 10 and 30 is incremented by one unit by the counters 14 and 32 under the control of the circuits 12 and 34. Then, the analysis of the first line of image continues with for example the meeting of the first point of a second defective column The address of this second column present in the register 18, is recorded at the second position of

  At the end of the first line, the colon addresses

  Faulty integers are in RAM memory.

  Irrespective of the mode of recording in volatile memory

  tile RA, here is then explored with a cyclic period which corresponds to the scanning frequency of a line (Fb), ie the counter 32 is reset at each beginning of line

  to return to the first memory location RLM.

  The output of RA> 30 is connected to a

  paratrix 38 which furthermore receives the current column address of the point explored by the signal processing circuit. When there is coincidence between the contents of the memory and this column address, a correction command is provided by the comparator 38 , through porze OR 28, at exit S of the circuit, and an order

  incrementation of the counter 32 is given to the circuit 34.

  Thus, from the second scanning line, and at each subsequent line until the end of image scanning, the column address of the first defective integer column is provided by the RAM 30. is encountered, a correction command is given, the counter 32 is incremented and the following defective column address is given At the end of

  the line, the counter 32 is systematically reset.

  This procedure continues independently of the search from the PROM 10 and the comparators 22 and 24, isolated defective points, the PROM memory being reinitialized only at the end of the image scan (Fi frequency )

  and not the line scan (frequency Fh).

  It should be noted that this circuit makes it possible easily to correct, if desired, an entire line of defective points, by entering in the PROM memory 10 only the address of the first

  point of that line or the address of that line alone, in indi-

  as for a specific additional bit that it is a li-

  This bit can be transmitted to the circuit

  signal processing to control the replacement of the correct signal

  responding to the entire line by the delayed signal of the first line

  or the average of the previous line and the next line.

Claims (4)

  1 signal processing circuit for photo analyzer   sensitive matrix, comprising a control circuit for correcting   detection of permanent localized defects of the analyzer, said control circuit comprising a programmable non-volatile memory (10) containing defective dot addresses, and a first comparator (22, 24) for comparing the contents of the memory ( 10) to a current point address explored by the signal processing circuit and to provide a correction control signal if there is coincidence between that content and that address, characterized in that the correction control circuit comprises in addition: a volatile memory (30) coupled to the output of the non-volatile memory (10) so as to allow the recording in the volatile memory of the addresses of entire defective columns contained in the non-volatile memory, a second comparator ( 38) for comparing the contents of the volatile memory with a current column address searched, and for providing a correction control signal if there is a coincidence between that content and that e address, a control circuit (32, 34) of the volatile memory for incrementing the addressing of the volatile memory after each co Incidence detected by the second comparator and reset to an initial value this addressing each line searched, and to perform the recording in the volatile memory of the addresses   whole columns defective.   2 signal processing circuit according to the   1, characterized in that the control circuit of the volatile memory cyclically records the addresses of entire columns defective after each image scan.   3 signal processing circuit according to the   2, characterized by the fact that the addresses of faulty whole columns are stored in non-volatile memory in words the 'having a specific bit indicating that they are columns defective whole.   4 Signal processing circuit according to one of   claims 2 and 3, characterized in that   the recording in the volatile memory is done during the   scanning the first line of the analyzer.   Signal processing circuit according to claim 2, characterized in that a sequencer (36) is provided to control systematically during the return period.   frame of the image scan, the transfer of the colon addresses   from non-volatile memory to volatile memory.