FR2512999A1 - SEMICONDUCTOR DEVICE FORMING PROGRAMMABLE DEAD MEMORY WITH TRANSISTORS - Google Patents

Abstract

INTEGRATED DEVICE INCLUDING IN PARTICULAR AN XY MEMORY MATRIX AND A DECODING ASSEMBLY OF WHICH THE TRANSISTORS ARE DISTRIBUTED IN HOUSINGS OF A SEMICONDUCTOR PLATE 20 LATERALLY LIMITED BY A DIELECTRIC CORD 23. THE EMITTER REGION 25A OF THE TRANSISTORS 11 OF THE MATRIX DIELECTRIC CORD 23, WHILE THAT 25B OF THE TRANSISTORS 14 OF THE DECODING ASSEMBLY IS REMOTE. APPLICATION TO MEMORIES WITH PROGRAMMABLE TRANSISTORS.

Description

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  "SEMICONDUCTOR DEVICE FORMING DEAD MEMORY

PROGRAMMABLE TO TRANSISTORS "

  The present invention relates to a semiconductor device

  integrated circuit including in particular a matrix of

  at least XY moire and a set of complementary circuits

  matrix, including a subset of deco-

  wherein said memory is capable of programming said memory via the PN junction breakdown (s), which memory and at least which subset each comprise a plurality of vertically structured transistors created

  in a semiconductor wafer and distributed in

  limited laterally by a dielectric cord, the

  which transistors present, in the vertical direction at least,

  dimensional and physical characteristics

identical.

  The invention 1 in the context of the programmatic dead-memories

  transistors, concerns all devices of this kind

  can be programmed electrically, as for example decoding sets or logic circuits, often

associated with memories.

  By the expression "set of complementary circuits of said matrix" employed above, it is necessary to understand subsidiary circuits which are functionally linked to the memory, made 3 s on the same semiconductor crystal as the latter and which make it possible, for example, to read , the writing at the moment of

  programming, signal addressing and their amplification

  On the other hand, the expression "dimensional characteristics"

  physical and substantially identical "implies that

  they are transistors made according to an opera-

  common territory and whose corresponding regions therefore have

  substantially equal thicknesses, whereas the nature of the

  and levels of concentration in these same impurities

  in these corresponding regions are also comparable.

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  -2- Make the transistors of the memory matrix and those

  various subsets of the device simultaneously pre-

  has a certain interest from the point of view of manufacturing.

  But the similarity between the transistors makes the program

  the more delicate matrix to achieve in fact, the junctions-which must be "slammed" in

  the transistors of the memory matrix have the same tendencies

  than those of the transistors of the said sub-

  sets, in particular those of the sub-set of deco-

  which are intended to guide the impulses

  Also, should a disparity be created that

  make sure that the breakdown voltages are relatively

  on the transistors side of the memory array.

  For this purpose perhaps, but also for reasons of reduction of the energy necessary for the breakdown at the same time

  save time in programming, it has been proposed

  different structures, for the transistors of the

  memory, which facilitate the breakdown.

  A transistor studied in this spirit is described in US Pat. Nos. 4,145,702 and 4,154,949. In this transistor, a double contact is made on the emitter region: on the one hand, the normal metallic contact electrically connected to the circuit on the other hand the contact of a small strip of metal (aluminum) which is left "in the air" and whose material contributes to the formation of a short-circuit path in the silicon during breakdown C ' is a provision found in other patents or

  In addition, the implementation, for the realization

  transistor, a technique known in the semiconductor industry, known as a "washed transmitter", allows the

  two aforesaid contacts are arranged very close to the

  base-emitter combination The combination of the two layouts allows energy and breakdown time to be reduced

  in a large proportion compared with the trans-

  tors de matrices memories according to the prior art.

  A first disadvantage of using transistors of the model as described above is the risk of a

  breakdown not initially programmed from the transmitter junction.

  base and which occurs spontaneously over time (the junction and the aluminum strip being very close to each other) by the effect of the solubility of silicon in aluminum according to a diffusion reaction at solid state, a phenomenon which manifests itself significantly even at a relatively low temperature Another disadvantage

  lies in the need to achieve different

  memory-related circuits which, in turn, must have good resistance to breakdown. In addition, the presence of said small metal strip on the transmitter region of the

  memory transistors increases the difficulty of

tion.

  The present invention makes it possible to remedy these incon-

  In particular, it provides a simple solution to

  problem of the necessary differentiation between

  sistors of a memory array and those of subsets

  associated, including the subset decoding.

  According to the invention, a semiconductor device such

  defined at the beginning of this memo, is particularly noteworthy

  in that the emitter region of the transistors of the memory array confines to said dielectric cord, while that of the transistors of said complementary circuits and, in particular, those of the decoding subsystem, in

is distant.

  The invention takes advantage of, on the one hand, the particular form

  the so-called "bird's beak", which takes, in the vicinity of

  the surface of a silicon wafer, a dielectric cord

  deep silicon oxide test carried out in a crucible

  on the wafer, by oxidation of the material of this wafer, on the other hand the fact that the concentrations of impurities in the silicon in the immediate vicinity of the bead are locally modified because of the presence of this

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  cord, to obtain conditions favorable to a fall-

  the breakdown voltage of junctions formed in the

neighborhood of said cordon.

  Since a difference can be obtained in

  between two locations of a silicon layer, it is sufficient, between two otherwise similar transistors, to place the one of which it is desired that it has the lowest breakdown voltage - in this case, the transistor of the memory array in the region of the adjacent layer of the dielectric cord and the transistor which is expected to

  better hold-in this case, the sub-transistor

  seems to decode in a remote area of this cord.

  The simplicity of structure and the simplicity of

  are the advantages of the device according to the invention.

  It suffices to play on the geometry of the masks as regards the locations of the emitter and base regions relative to the lateral dielectric cord.

  to obtain the desired dissymmetry between the

  tors of the two sets considered.

  Various alternative embodiments of the device according to the invention are possible, which aim to introduce more or less marked dissimilarities between the transistors.

  of each type> dissimilarities which result in different

breakdown voltage faults.

  Thus, it can be done that the base region of the transistors of the memory array, on a more or less long fraction of its perimeter, confines along its entire thickness to the dielectric cord The cord then cuts the deep part, parallel to the surface, of the junction

base-collector.

  It can be done also that this same base region of the transistors of the memory array, also on a fraction more or less long of its perimeter, confines only on a part of its thickness to the dielectric cord So, the cord, in said fraction, does not cut the deep part, parallel to the surface, of the collector junction, but only the lateral part,

  curved towards the surface of this junction.

  This provision aims at reducing the emitter-base and base-collector breakdown voltages of these transistors as well as

  than the breakdown energy needed.

  In the context of each of the two above variants, it can be done that the basic region of the transistors of the decoding subassembly confinesur a part of its thickness at least and over a fraction more or less long of its perimeter, at the dielectric cord It can be done

  also that this base region is distant from said bead.

  The description that follows, next to the drawings

  annexed, will make it easier to understand what the invention

in its various aspects.

  Figure 1 illustrates, very schematically, the

  of a semiconductor device forming a read-only memory

  programmable to which the invention relates.

  FIG. 2 shows, arranged side by side, in section vi (FIG. 2A, axis II-II of FIG. 2B) and in plan (FIG. 2B), a transistor of the memory matrix according to FIG.

  first embodiment and another transistor of the dis-

  positive, in particular a transistor of the decoding subsystem.

  FIGS. 3 and 4 show, again according to a sectional view on the one hand (FIG. 3A, axis III-III of FIG. 3B) and a plan view on the other hand (FIG. 3B), a transistor of FIG.

  memory array according to a second embodiment.

  FIG. 4 is an enlarged sectional view of the portion

  of Figure 3 located near the lateral dielectric cord.

  It should be noted that> in the figures} the dimensional ratios

  realities have not been respected;

  this, in order to ensure that these figures have the necessary clarity

thinkable.

  In the schematic device of FIG.

  are symbolized in the form of quadrilaterals, two of

  components of a programmable memory array.

  A first rectangle 10 represents the memory matrix itself, which comprises a plurality of line conductors X 1, X 2, X 3, and Y 1, Y 2, YV columns isolated from each other at the crossings. which cells are connected each constituted by a transistor 11, for example NPN type; the emitter of each transistor is connected for example to a line conductor X, while the collector is connected to a column conductor Y, the base remaining in the air or can be connected for

programming needs.

  A second rectangle 12 represents one of the subassemblies

  devices, associated with the matrix 10; it is notably the decoding subassembly, connected to the XY matrix and which intervenes for the programming The transistors

  14 of NPN type that equip this set can be

  nected in various ways to form said assembly; the

  link scheme was not traced.

  All this is well known to those skilled in the art and has been drawn only to situate the scope of the invention, invention

  which relates to transistors 11 and 14.

  The required performance of transistors 11 and 14 means that they can be made according to an identical model or

  very neighbor; their realization is therefore carried out simultaneously

  It remains to differentiate them in terms of resistance to breakdown, the transistors 14 of the decoding subassembly must imperatively have a better behavior than those,

11, of the memory matrix.

  Referring now to FIGS.

  in section and in plan, respectively of a transistor 11 and a transistor 14, showing how the difference

  desired is obtained between these two transistors.

  These transistors 11 and 14 were created in the same semiconductor wafer 20 composed of a substrate 21 of a

  first type of conductivity covered with an epitaxial

  xiale 22 of the second type of conductivity and having -7-

  an upper face 200 which is the active side of this pla-

  that all components and on the

  The said transistors are distributed in caissons limited laterally by a dielectric bead 23 and, in depth, by a buried layer 26 of the second type of conductivity (the presence of this layer is not imperative). 'a

  and the other, a collector region consisting of the

  22, a base region 24 of the first type of conductive

  and a transmitter region 25, of the second type of con-

  ductivity, included in basic region 24 (for the facilitation

  In accordance with the distinction between 24 A and 24 B respectively, the basic regions of the transistors 11 and 14, 25 A and 25 B respectively are designated as their respective emitter regions.) Contact pads 220, 250, 240 , (220 A,

  250 A, for transistor 11, 220 B, 250 B, 240 B for the tran-

  sistor 14) allow electrical access respectively to the collector, emitter and base regions t the latter

  contact being optional for the basic driver of the tran-

  sistor 11, no 240 A contact pad has been drawn.

  Transistors 11 and 14, because of their simultaneous embodiment, have in the vertical direction (along an axis traversing the wafer in thickness), dimensional and physical characteristics very substantially identical

  the thicknesses of the emitter, base, collector regions

  are the same; conductivity types and impurity concentration gradients at equal level of

  depth in the wafer are also the same.

  To get a significant difference on the map

  resistance to breakdown, it is necessary to create a dissimilarity

  the horizontal direction: according to the invention, "the

  Transmitter region 25A of transistors 11 of the memory array is confined to said dielectric bead 23, while that (25B) of transistors 14 of the decoding subassembly 12 in FIG.

is distant ".

  As recalled in the first part of this specification, the zone of the semiconductor layer 22 adjacent to the dielectric cord 23 is an area where the impurity concentrations are disturbed and which is weakened in terms of breakdown resistance. when> it is clear that it is in this area that the transistors 11 will snap, at a voltage

  for which the transistors 14 will still hold perfectly.

  To concentrate the breakdown energy, it is advantageous for the transmitter A to be confined to the cord 23 only a short distance from its perimeter; this explains that, in the figures) the transmitter 25 A touches the cord 23 only on the small side

  of its outline and not according to its length.

  Various embodiments are possible which establish dissimilar dissimilarities between transistors 11 and 14 and which result in differences between the emitter-base, base-collector and emitter-collector breakdown voltages.

of these transistors.

  Thus in the transistors of FIG. 2 and for a first

  first embodiment of the base regions 24 A and 24 B con-

  both end on their entire thickness and on the largest fraction of their perimeter to the dielectric cord 23; only the transmitter regions 25 A and 25 B are dissimilar

  in position relative to said cord.

  According to another embodiment, it is possible for the base region 24 B of the transistor 14 to be distant from the cord

  This variant corresponds to line 27 in

  2> a marked difference in breakdown voltage between transistors 11 and 14 will be observed either

  and on base-collector and transmitter-transmitter-base voltages

manifold.

  The variant embodiment of a transistor 11 which allows

  to obtain the greatest reduction of its tensions of

  quage corresponds to that illustrated in Figures 3 and 4.

  In this variant the invention exploits both the

  disturbances of the semiconductor material in the vicinity of the cor-

  don 231 and the shape of this cord to obtain a lowering

  very clear emitter-base and base-pass breakdown voltages

  transistor 11 compared to those of the transistors

twist 14.

  9- The shape of the dielectric cord is characteristic

  of that obtained by oxidation of the walls of a hollow groove

  It is superfluous to return here to the conditions of realization of such a cord-conditions well known to those skilled in the art and, with regard to

  invention, it suffices to stick to the result: the cor-

  don 23 has the shape called "bird's beak", the oxide connection

  of silicon-silicon, considered from the bottom of the cord

  the surface, being marked by a flaring of the o-xyde and generally having an extra thickness on the surface 230. In the variant embodiment of a transistor 11 which corresponds to FIGS. 3 and 4, the base region 24 A , as the emitter region 25A, only confine on only a portion of their thickness to the cord 23 Said cord 23

  only then cuts the lateral parts 34 and 35, incur-

  in the direction of face 200, respectively

  J 1 (transmitter-base) and J 2 (base-collector), to the ex-

  clusion of the deep portions, parallel to the face 200, of these junctions The inter-region 36 base, located between the side portions 34 and 35 forms a narrow band whose most strangled area is located in the vicinity of the cord

  23 It is in this area 36, weakened both in size and

  and as a material (concentration of impurities) that will preferably occur the discharge leading to breakdown of one or the other emitter-base junctions

  or base-collector of the transistor II at the moment of the

grammar of memory.

  The flared shape of the cord 23, which constitutes, in itself, a defect of the oxide-insulated devices, because of the flatness irregularities which it causes, is used here with advantage, however, as shown on FIG.

Figure 4.

  It has been assumed, for example, that the regions 24 A and 25 A are formed by implantation, as is frequently the case in the integrated circuit industry as far as the realization of the marginal parts of the circuits is concerned.

  regions 24 A and 25 A as shown in FIG.

  it is the cord 23 itself that fulfills the role of implantation mask The thickness of the "bird's beak" 230 gradually decreasing towards the right of the figure,

  that is, as it fades, the depths of

  planting grow regularly; this is what the oblique lines, located under the so-called "bird's beak" translate, lines 41 and 42 appearing respectively, for the impurities

  and for transmitter impurities, the limits of

  planting of these impurities The non-parallelism of these oblique lines, linked in particular to the differences of the energies

  put into play for each of the impurities as well as to the

  of these, results, after the annealing which follows the implantation sequences, an irregular width of the base area 36 between the emitter-base junctions J 1 and base-collector J 2 'the smallest width being at

immediate vicinity of the cord 23.

  Practically and according to an example of realization put

  implemented by the Applicant, we first implant the ar-

  senic to form the transmitter region, this under a

  about 30 ke V; then implanted boron (base region) under an energy of the order of 40 ke V; finally, annealing is carried out at 7500 C for 30 minutes. Under these conditions, the collector-emitting breakdown voltage in zone 36 is around 6 V; it is close to 10 V for the decoding transistors made under energies

identical implantation.

  The implantation process may be substituted for that of

  diffusion, the groove 23 always playing the role of mask.

  To influence the result, you can play on

  several factors, including the conditions for

  sion or implantation, and also on the shape of the

  bucket "which can be more or less thick and tapered, which

  gives some flexibility to the realization.

  Certainly, between the various transistors 11 of a memory array made simultaneously, said zone 36 is not strictly comparable in width and the breakdown levels are they a little different But the goal to be achieved here n ' is not so much to reduce the dispersion between transistors 11 as to establish the most marked dissimilarity between these transistors and transistors 14 of the decoding set, in the course of course, a perfect consistency with the requirements

  of operation of the semiconductor device which

  globe It is also certain that it is the structure of a transistor 11 corresponding to FIGS. 3 and 4 which makes it possible to have the lowest breakdown voltages and which therefore makes it possible to reach the lowest energies involved and

  at maximum speed during programming.

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Claims (5)

-REVENDICATIONS -   l. Semiconductor device with integrated integrated circuit   carrying in particular at least one XY memory array and a set of complementary circuits of said array, including in particular a decoding subassembly making it possible to program said memory by means of the PN junction breakdown (s), which memory and   at least one subset   of vertically structured transistors created in a semiconductor wafer and distributed in laterally limited boxes by a dielectric bead, which transistors have in the vertical direction at least substantially identical dimensional and physical characteristics, characterized in that the emitter region of the   transistors of the memory array confined to said   while that of the transistors of said complementary circuits and in particular those of the subset of decoding, is remote.   2. Semiconductor device according to claim 1, characterized in that the base region of the transistors of the memory array, on a more or less long fraction of its perimeter, confines according to its entire thickness to dielectric cord.   3. semiconductor device according to claim 1, characterized in that the base region of the transistors of the memory array, on a more or less long fraction of its perimeter, confines only on a part only   from its thickness to the dielectric cord.   4. Semiconductor device according to all the   2 and 3, characterized in that the base region of the transistors of the decoding assembly is confined, at least in part of its thickness and at a fraction higher than   or less of its perimeter, to the dielectric cord.   5. Semiconductor device according to all the   Claims 2 and 3, characterized in that the base region of the transistors of the decoding set is distant dielectric cord.