FR2512603A1 - Voltage divider bridge for high speed MOS inverter - uses semiconductor component in each arm operated in negative impedance region by pulse generator - Google Patents

Abstract

The arrangement has a voltage divider bridge comprising two arms (B1,B2) one (B1) of which contains an impedance (9) whose value is adjusted by a control circuit (4). This impedance is in parallel with a semiconductor component (10). The second arm (B2) contains another semiconductor component (11) which acts as its impedance. The two semiconductor components are connected to a pulse generator (5) to ensure they operate in the negative impedance area at instants when the bridge ratio is being changed. The two semiconductors are mounted head to tail to ensure that pulses of a given polarity act on one or other as required. When a load is connected to the circuit a very fast switching action is obtained due to the high current which passes through the semiconductor components.

Description

REPORTING VOLTAGE DIVIDER BRIDGE
COMMANDABLE AND APPLICATION TO ELECTRO INVERTERS
DOMINIONS
The invention relates to a controllable ratio voltage divider bridge of the electronic bridge type comprising two branches provided with impedances, one of which is variable and controlled. It extends to the applications of this bridge, in particular for producing electronic inverters with very low switching times.

 Several types of electronic inverters are known that make it possible to dispose at the output of a voltage complementary to the voltage applied at the input; when they are coupled at the output to a strongly capacitive load, these inverters have the disadvantage of being subjected to the following alternative: either the switching takes place very slowly in these inverters (greater than 1 microsecond in the case of a MOS technology inverter coupled to a load of 100 pico Farad), or if it is desired to reduce the switching time, the power consumed is significant and is dissipated continuously both during the transient periods and during stationary periods.In addition, in the latter case, and if the technology used is a MOS technology (Currently the most common case), the signal transistor has a greatly increased size and very penalizing.

 To overcome these drawbacks, it is possible to use an optimized reversing channel (of 7 inverters) which makes it possible to significantly reduce the switching times and to reduce them to values of the order of 50 nanoseconds in the above-mentioned case of inverter reversers. MOS technology, coupled with loads of the order of 100 pico Farads; however, the area occupied on the silicon chip becomes about 2000 times larger than in the case of a single inverter. At present, this solution is often chosen, but it proves to be more and more disadvantageous in the growing reduction in the dimensions of the integrated electronic components.

 The present invention proposes to create a solution constituting an excellent compromise between the duration of the switching times, the power consumed and the occupied surfaces.

 An object of the invention is in particular to allow, in M.O.S. technology, switching times of the order of tens of n, -mosecond for loads of several hundred pico Farads.

 Another objective is to provide a device that consumes significantly energy only during transient periods of switching so that the average energy dissipated is extremely low.

 Another objective is to provide an inverter whose size is of the same order of magnitude as that of an inverter M.O.S. classic.

 For this purpose, the electronic inverter according to the invention is constituted by a controllable ratio voltage divider bridge, new type hereinafter defined.

 Of course, the invention extends to the divider bridge itself as such, regardless of its application; this bridge can in particular be used to charge or discharge capacitive circuits in other applications.

The divider bridge targeted by the invention is of the type comprising a first variable impedance branch controlled to fix the ratio of the bridge, a control circuit of said variable impedance driven by a signal of eneu, a second branch of determined impedance, arranged in series with the first branch, a source of teuton at the terminals of the two branches and a mid-point of exit; according to the present invention, the bridge is characterized in that
at least one of the branches of the bridge comprises a semiconductor component constituted by a junction
PN in series with one or more auxiliary layers adapted to impart to said semiconductor component, when biased through a resistor, a current / voltage characteristic across its terminals comprising a negative impedance area separating two positive impedance zones of which one one (e) corresponds to a bias voltage lower than one threshold and the other to a bias voltage higher than this threshold (V5),
said semiconductor component is associated with synchronous pulse generating means of the aforementioned control circuit, said generating means being adapted to deliver at the terminals of the component, at times of change of the ratio of the bridge, voltage pulses such as the magnitude of the voltage across said semiconductor component rises above the threshold (Vs).

Thus, during a switching triggered by the control circuit under the influence of the input signal (e), two types of effects occur in the bridge
a variation of the variable impedance, as in the case of a conventional divider bridge,
and a sudden change in the impedance of the semiconductor component from one positive impedance area (R +) to the other positive impedance area (r +) across the negative impedance area (r-).

 This second effect controlled by the pulse generating means causes, during the transient switching period, the appearance of a charge or discharge current of very high intensity, whereas outside these transient periods, this current remains weak. Thus, the device makes it possible to switch high amounts of energy in very short times without consuming substantially power in stationary mode.

According to a preferred embodiment which gives the device a small footprint and makes it compatible with a standart MOS technology, the variable value impedance, the control circuit of this impedance and the pulse generating means are formed by a transistor
MOS (Metal Oxide Semiconductor) having a gate capacitance driven by the input signal / for controlling the impedance variations of said MOS transistor and having a gate-drain overlap capability, coupled to each semiconductor component aforementioned and of suitable value to allow the generation of the aforementioned pulses under the effect of variations of the gate voltage.

 The aforementioned semiconductor component may take various embodiments to achieve the current / voltage characteristic previously defined.

A structure (known in itself) particularly adapted for said component consists in arranging the PN junction already mentioned in series with a semi-insulating layer (composed in particular of silica or polycrystalline silicon or nickel fluoride or aluminum nitride) and a metal layer (in particular aluminum, gold or chromium), these layers being deposited successively on one of the layers of the PN junction.

It should be noted that by "semi-insulating" is meant any layer that allows a passage of electrons and a control of the electron current flowing between the metal layer and the valence band of the contiguous layer of the PN junction. This "semi-insulating" property can in particular come not only from the nature of the material but also from its thickness and any impurities contained therein.This layer may in particular be constituted by a pure insulating material in very small thickness ( less than 100 Angstroms), or by a pure polycrystalline semiconductor, of greater thickness (of the order of several hundred Angstroms) or by a thick layer insulating material containing impurities or by a conductive material ionic low conductivity
As the invention has been explained in its general form, other features, objects, and advantages thereof will become apparent from the following description with reference to the accompanying drawings, which show embodiments thereof, as well as examples which have been disclosed. object of experimentation: on these drawings which are an integral part of the description
FIGS. 1, 2 and 3 are symbolic diagrams of three embodiments of dividing bridges according to the invention,
FIG. 4 is a schematic sectional view of a semiconductor component of the NISS type (mental
Semi-Insulator, Silicon, Silicon) particularly suitable for equipping the divider bridges according to the invention or their applications,
FIG. 5b illustrates the current / voltage characteristic of this semiconductor component when it is polarized according to the diagram of FIG. 5a,
FIG. 6 represents the electrical diagram of an inverter having been the subject of the experiments referred to in example 1 below,
FIGS. 7a and 7b are diagrams illustrating the performances of this inverter,
FIG. 8 and FIGS. 9a and 9b relate to another inverter referred to in example 2 below,
- Finally, Figure 10 and Figures Ila, llb and llc relate to another inverter, referred to in Example 3.

 For ease of understanding, the figures show the same references for the common parts of the various modes or examples of embodiment.

 The divider bridge embodiment shown in FIG. 1 comprises two branches: a first branch B1 containing a conventional type 1 impedance of adjustable value, and a second branch B2 containing a semiconductor component 2 which is described below and form the impedance of this branch.

 The two branches B1 and B2 are arranged in series with respect to a voltage source symbolized in U and the output of the divider bridge is located in s between the two branches B1 and B2.

 By "conventional type impedance" is meant any known component having a positive impedance of known value; in the case of the embodiment currently described, this impedance has a variable value and may in particular be constituted by a variable resistor or a transistor M.O.S. (Metal Oxide Semiconductor).

 In known manner, this impedance is controlled by a control circuit 4 which triggers the variations of its value. This control circuit is driven by an input signal e which triggers it; the input of the circuit 4 constitutes the input e of the divider bridge (or the application device which is derived therefrom).

 The semiconductor component 2 (designated as M.I.S.S. in the diagrams) is essentially constituted by a PN junction in series with auxiliary layers which are adapted as will be seen more precisely later, to give said component a negative impedance zone.

 This component 2 is associated with means 5 for generating pulses, which are synchronized with the aforementioned control circuit 4. These means are adapted to deliver at the terminals of the component 2 voltage pulses at times of change of the ratio of the bridge (variation of the impedance 1) so that the negative impedance area is reached during the appearance of said pulses.

 In the example of FIG. 1, when the impedance 1 increases abruptly by the action of the control circuit 4 and induces an increase in the output voltage S, the pulse from the means 5 causes the component 2 to operate. in a zone of negative resistance, thus allowing the passage of a very high current in said component 2.

 When the bridge is coupled at the output to an external circuit to be charged, the passage of a high current in the branch B2 generates a very fast switching of the output voltage s, even when the circuit to be loaded has a high load capacitive. Indeed, the charging time (ie the duration of the switching) varies directly as a function of the ratio of the capacity of the external output circuit to the intensity of the current available during charging.

The control circuits 4 and generation means 5 can be of various shapes; as we will see, they can in MOS technology form only one element with the classical impedance 1 (suitably chosen to
This effect).

 The embodiment shown in FIG. 2 has a general structure analogous to the previous one and this figure shows the essential elements shown in FIG. 1: branch B1, branch B2, output s, control circuit 4, input e, means pulse generation 5.

 In this example, the first branch B1 comprises, on the one hand, a conventional type impedance 6 of adjustable value controlled by the control circuit 4, on the other hand, a semiconductor component 7 of the same type as the component 2 and arranged in parallel with the impedance 6.

 The second free B2 contains an impedance of the classical type 8 of determined value (this impedance is in the fixed example but could be variable and controlled).

 In this embodiment, when the impedance 6 decreases abruptly by the action of the control circuit 4 and induces a decrease in the output voltage s, the pulse from the means 5 causes the component 7 to operate in a zone of negative impedance, thus allowing the passage of a very high current in said component 7.

 When the bridge is coupled at the output to an external circuit destined to be discharged, the passage of a high current in the component 7 generates a very fast switching of the output voltage even when the circuit to be discharged has a high capacitive load. .

 Thus, the bridge of Figure 1 allows a very fast switching in the case where the external circuit is loaded during it and the bridge of Figure 2 performs the same function in the case where occurs a discharge of the external circuit .

FIG. 3 shows an embodiment making it possible to obtain a fast switching both in the case of the load and in that of the discharge of an external circuit. This embodiment, which represents a synthesis of the two previous ones, is characterized in that
the first branch B1. comprises, on the one hand, an impedance of conventional type 9 of adjustable value, controlled by the control circuit 4, on the other hand, a semiconductor component 10 as mentioned above, arranged in parallel with said conventional impedance type 9 ,
the second branch B2 contains another semiconductor component 11 as mentioned above, which constitutes the impedance thereof,
the two semiconductor components 10, 11 are associated with pulse generation means of the above-mentioned type, adapted to cause each of said components to operate in the negative impedance zone at times of change of the ratio of the bridge.

 In addition, the components 10 and 11 are mounted head-to-tail with respect to each other so that the pulses of a given sign play on one of the two and the opposite-sign pulses play on the other. other component.

 When charging the external circuit, the switching takes place in a very short time thanks to the high current flowing through the component 11 and during the discharge, the switching is also carried out in a very short time thanks to the high current flowing through the component 10.

 FIG. 4 illustrates a preferred embodiment of a semiconductor component such as the one mentioned above. Such a component is particularly suitable for a M.O.S. but can also be used in other embodiments of the circuits.

 This component of the type M.I.S.S. comprises a silicon substrate 12 of the P or N type, a N or P-type silicon layer 13 forming a PN junction with the substrate, a silica layer 14 deposited on the layer 13 and a metallic layer 15, in particular a layer aluminum.

 The silicon layer 13 has in the example a thickness of 5 to 10 microns, the silica layer 14 a thickness less than 100 Angstroms and the metal layer 15 a thickness of a few thousand Angstroms.

 In the experiments described in Examples 1, 2, and 3 described below, the metal layer 15 forms an electrode having a diameter of about 160 microns.

 The current / voltage characteristic of this component can be analyzed in a simple way by polarizing it through a resistor as shown in the diagram of FIG. 5a where the semiconductor component is designated by the reference 16 and the resistance by the reference 17. The bias voltage is noted P, while the voltage appearing across the component 16 is noted V and the current flowing through the component is noted i.

 FIG. 5b represents, on the one hand, in solid and discontinuous lines, the current / voltage characteristic i (V) of the component, on the other hand, in dashed lines, the variations of the current i (P) as a function of the variations of the bias voltage P applied.

The current / voltage characteristic i (V) of the component is characterized by the presence of three zones
a positive impedance R + zone (of the order of a few tens of kiloohms in the example) when the polarization voltage P is below a threshold
Vs (of the order of a few volts),
a zone r of negative impedance which is crossed when the polarization voltage P becomes greater than Vs,
and a r + zone of positive impedance (of the order of a few hundred ohms in the example) which follows the zone r when the polarization voltage P continues to rise beyond Vs.

 In the device of the invention, the component operates in its R + zone outside the transient switching periods and operates in the zones r and r + during the brief switching periods. Thus, the average power dissipated is very small since the equivalent resistance of the component has a low value only during transient periods of switching.

Examples 1, 2 and 3 given below illustrate with reference to FIGS. 6 to 11c the operation and the performance of inverters according to the invention constituted respectively by bridges of the type of those of FIGS. 1, 2 and 3, equipped with of components
the type of that of Figure 4, the current / voltage characteristic has the shape of that shown schematically in Figure 5b as mentioned above (Figure 4).

EXAMPLE 1
This example relates to an inverter whose electronic diagram is provided in Figure 6; a transistor
MOS 18 forms, both the variable impedance of the branch
B1 (constituted by the resistance of the transistor channel), the control circuit thereof (consisting of the gate capacitance of the transistor) and the pulse generating means (constituted by the gate-drain capacitance of the transistor ).

For this purpose, the transistor 18 is mounted so that its gate capacitance is driven: by the input signal e and its gate-drain overlap capacitance is coupled to the semiconductor component 19 of the branch B2 (component of the previously described MISS type). Moreover, the
The values of the characteristics of the transistor 18 are chosen so as to enable, under the effect of the variations of the voltage of the gate e, the generation of pulses of sufficient amplitude to raise the voltage across the semiconductor component 19 beyond the threshold value Vs thereof.

In addition, for the device to be able to fulfill its function of inverter, the transistor 18 and the semiconductor component 19 are chosen so that the following relationships are satisfied.
VS) U (l - Ron
R + Ron
Ron. g (VUR + Ron T where: U is the supply voltage across the two branches
B and B2,
Ron the transistor 18 channel resistor,
VT the threshold voltage of transistor 18,
VS the threshold voltage already mentioned for component 19,
R + the positive impedance already mentioned of said component 19.

 Respecting these relationships conditions the stability of the logic levels high and low at the output s.

The operation and performances that are commented below have been obtained with the following parameters
- supply voltage U = 3 volts
threshold voltage Vs = 2.1 volts
R + impedance of the component 19 = 50 kilo ohms
impedance r + = 200 ohms
- MOS transistor 18 having the characteristics
following ones: Ron = 30 kilo ohms
V = 2 volts
The inverter was coupled to an external load of value equal to 100 pico farads.

FIG. 7a shows, as a function of time, the input signal e applied to the gate of the transis tor 18 and the consequent variations in the output voltage s. First of all, the device fulfills the role of an inverter since the signals e and s are complementary to the dental
FIG. 7a also gives, as a function of time, the variations of the current I supplied by the power supply.
U. It can be seen that the current I remains very low outside the transient load period of the output capacitance.

Figure 7b is an expanded time scale diagram showing the F1 front of the signals during charging. Since the input front has a descent time of about 25 nanoseconds, it can be seen that the corresponding rise time of the output signal s does not exceed 50 nanoseconds, which represents an exceptional performance for an inverter only coupled to a load of 100 pico
farads
Moreover, this FIG. 7b confirms that the current is negligible during the stationary phases, and this, while the charge current is very high during the transition (of the order of 5 milliamperes): consequently, the energy consumed by the inverter (apart from that used to charge the external circuit) is negligible.

 Similar tests were performed on an output load of 230 pico farads: the switching time was then of the order of 70 nanoseconds.

EXAMPLE 2
This example relates to an inverter whose electronic diagram is provided in FIG.

The branch B1 includes a transistor
MOS 20 in parallel with a semiconductor component 21 (of the MISS type previously described). The transistor, O, S.

20 forms both the variable impedance of the device control circuit thereof and the pulse management means, in the same manner as the transistor 18 in the previous example.

 For this purpose, the transistor 20 is mounted so that its gate capacitance is driven by the input signal e and its gate-drain overlap capacitance is coupled to the semiconductor component 21.

 In its second branch B2, the inverter comprises a transistor M.O.S. 22 mounted in charge transistor, that is to say with its gate connected to the drain; it thus defines a current lo when it is subjected to a drain-source voltage equal to the supply voltage U.

In order for the device to be able to fulfill its function as an inverter, the semiconductors 21 and transistor 22 are selected so that the following relationships are satisfied between their parameters.
Where V is the threshold voltage of transistor 20,
the positive impedance of the semiconductor component21
VS the threshold voltage of this component the current defined by the transistor 22.

 In the same way as before, the respect of these relations conditions the stability of the logical levels high and low at the exit s.

The operation and performances that are commented below have been obtained with the following parameters:
supply voltage U = 7.8 volts
threshold voltage Vs = 3 volts
impedance R + = 52 kilo ohms
impedance r + = ohms
threshold voltage VT of transistor 20 = 2 volts
defined by the transistor 22 = 50 microamperes
The inverter was coupled to an external load of value equal to 100 pico farads.

 FIG. 9a represents, as a function of time, the input signal e applied to the gate of the transistor 20 and the consequent variations in the output voltage s. As previously, it is found that the inverter function is performed, that the switching times (in this example for the discharge: F2 front) are very low and of the order of 50 nanoseconds (Figure 9 and that the current I pen the stationary phase remains below 30 micro-amperes.

 The same conclusions as above can be made with regard to the discharge of the external output circuit.

EXAMPLE 3
This example relates to an inverter whose electronic diagram is provided in Figure 10.

The branch B1 includes a transistor
MOS 23 arranged in parallel with a semiconductor component 24 (of the MISS type already described). Branch B2 is constituted by a semiconductor component 25 (of the MISS type

already described).

 The transistor 23 is mounted so that its gate capacitance is driven by the input signal e and its gate-drain overlap capacitance is coupled to the two semiconductor components 24 and 25 which are mounted head-to-tail. compared to each other.

In addition, for the device to be able to fulfill its function of inverter, the transistor 23 and the semiconductor components 24 and 25 are chosen so that their parameters satisfy the following relations
R +
(-------). U <VS1
(R + 1 + R + 1 + 2.

2
R l + R 2 2
+ 0 <VT <------- .U
R + 1 + R + 2
Ron
(1 - R + + -). u <Vs2
2 Ron 2
Ron + U <VT U
Ror. + R 2
where: VT is the threshold voltage of the transistor 23,
Ron the channel resistance of it,
V the threshold voltage of the semiconductor component 24
R1 its positive impedance for a lower polarization
above threshold Vs
V the threshold voltage of the semiconductor component 25
2
R2 its positive impedance for a lower polarization
above threshold Vs
U the supply voltage.

 Respecting these relationships conditions the stability of the logic levels high and low at the output s.

The operation and performance illustrated in FIGS. 11a, 1b and 1c were obtained with the following parameters:
V8 = 2.7 volts 2
V = 1.9 volts
U = 3 volts
VT = 1 volt
R1 = 50 kilo ohms
R2 = 75 --kiloohms
Ron = 13.5 kilo ohms
The inverter was coupled to an external load of 100 pico farads.

 Fig. 11b is an expanded time scale diagram showing the F3 fronts during charging and Fig. 11c is a similar diagram showing the F4 fronts at the discharge; the switching times are very low both at load and at discharge (of the order of 50 nanoseconds).

Claims (12)

 1 / - Controllable ratio voltage divider bridge, of the type comprising a first branch (B1) variable impedance controlled to fix the ratio of the bridge, a circuit (4) for controlling said variable impedance attacked by a signal d input (e), a second branch (B2) of determined impedance, arranged in series with the first branch (B1) a voltage source (U) across the two branches and an output midpoint (s) , said device being characterized in that  at least one of the branches (B1, B2) of the bridge comprises a semiconductor component (2, 7, 10 or 11) constituted by a PN junction (12, 13) in series with one or more auxiliary layers (14, 15) adapted to impart to said semiconductor component when it is biased across a resistor (17) a current / voltage characteristic across its terminals having a negative impedance area (r-) separating two positive impedance areas (R +, r ) one of which (/) corresponds to a bias voltage (P) less than one threshold (V8) and the other to a bias voltage (P) greater than this threshold (Vs),  said semiconductor component (2, 7, 10 or 11) is associated with means for generating synchronous pulses (5) of said control circuit (4), said generating means (5) being adapted to deliver at the terminals of the component, at times of change of the bridge ratio, voltage pulses such that the amplitude of the voltage across said semiconductor component rises above the threshold (Vs).  2 / - bridge divider according to claim 1, characterized in that only the second branch (B2) comprises a semiconductor component (2) asqueprécité, which constitutes the impedance thereof, the first branch (containing an impedance of conventional type (l) of adjustable value controlled by the control circuit (4)  3 / - divider bridge according to revendicawsion 1, characterized in that  the first branch 5Bli comprises, on the one hand, an impedance of conventional type (6) of adjustable value, controlled by the control circuit (4), on the other hand, a semiconductor component (7) asprepared disposed in parallel with said impedance of conventional type (6),  . the second free (B2) contains an impedance of conventional type (8) of determined value.  4 / - divider bridge according to claim 1, characterized in that:  . the first branch (B13 comprises, on the one hand, an impedance of conventional type (o) of adjustable value, controlled by the control circuit (4), on the other hand, a semiconductor component (10) as mentioned above arranged in parallel with said conventional type impedance (9),  the second free (B2) contains another semiconductor component (11) as mentioned above, which constitutes the impedance thereof,  the two semiconductor components (10, 11) are associated with pulse generating means of the above-mentioned type (5), adapted to raise the amplitude of the voltage across one or the other said components (10 or 11) above its threshold voltage (Vs) at times of change of the ratio of the bridge.  5 / - divider bridge according to one of claims 1, 2, 3 or 4, characterized in that the variable value impedance (1, 6 or 9), the control circuit (4) of this impedance and the means for generating pulses (5) are formed by a MOS transistor (Metal Oxide Semiconductor) having a gate capacitance driven by the input signal (e) for controlling impedance variations of said M.O.S. and having a bulk capacitance, coupled to each aforementioned semiconductor component and of suitable value to allow the generation of the aforementioned pulses under the effect of variations of the gate voltage.  6 / - bridge divider according to one of claims 1, 2, 3, 4 or 5, characterized in that each semiconductor component as mentioned above is constituted by a PN junction (12, 13) arranged in series with layers auxiliaries formed by a semi-insulating layer (14) and a metal layer (15) successively deposited on one of the layers (13) of the PN junction.  7 / - divider bridge according to claim 6, characterized in that each semiconductor component has a structure of MISS type, composed of a metal layer (15), a silica layer (14) allowing the passage of electrons , an N or P type silicon layer (13) and a P or N type silicon substrate (12).  8 / - electronic inverter for outputting a voltage complementary to an input voltage, characterized in that it consists of a divider bridge according to one of claims 1 to 7, the input being constituted by the input of the control circuit and the output by the midpoint of the bridge.  9 / - electronic inverter according to claim 8, characterized in that it comprises  in its first branch (B1), a transistor M.O.S. (18) having a Ron channel resistance and a VT threshold voltage,  in its second branch (B2) a semiconductor component M.I.S.S. (19) having a threshold voltage (Vs) and a positive impedance R + for a lower bias voltage (Vs),  said transistor (18) and said semiconductor component (19) being selected so that their parameters satisfy the following relationships  v U (1 - ~ Ron  R + Ron  Ron) U <VT SE  R + + Ron where U is the voltage of the power source across the two branches (B1 and B2).  10 / - electronic inverter according to claim 8, characterized in that it comprises  in its first branch (bu), a transistor M.O.S. (20) arranged in parallel with a semiconductor component M.I.S.S. (21), the transistor (20) having a threshold voltage VT, and the semiconductor component (21) a threshold voltage Vs and a positive impedance R + for a bias voltage less than the threshold Vs,  in its second branch (B2), a transistor M.O.S. charging device (22) defining a current lo when subjected to a drain-source voltage equal to the supply voltage U,  the transistor (20), the semiconductor component (21) and the transistor (22) being selected so that their parameters satisfy the following relationships  O <VT (R + lo <V8  11 / - electronic inverter according to claim 8, characterized in that it comprises  in its first branch (B1), a transistor M.O.S. (23) arranged in parallel with a semiconductor component M.I.S.S. (24), the transistor (23) having a threshold voltage VT and a channel resistor Ron and the semiconductor component (24) a threshold voltage VS1 and a positive impedance R1 + for a bias voltage lower than the threshold Vs1,  . in its second branch (B2) a semiconductor component M.I.S.S. (25t having a threshold voltage Vs and a positive impedance R2 + for a po bias voltage lower than Vs  2 ',  the transistor (23), the semiconductor components (24) and (25) being selected so that their parameters satisfy the following relationships  R + + + U <VS  R l + R 2  R + (1 - R J U (VS  R + 1 + R 2  +  1  O <VT <R + 1 + R + U  2  (1 - Ron) <Vs2  R + 2 + Ron  Ron U # VT # U  Ron + R + 2  12 / - Application of an electronic inverter according to one of claims 8, 9, 10 or 11, characterized in that the inverter is connected at the output (s) to a high capacity stage to achieve the load or the discharge of this floor in very short time.