FR2498836A1 - Load shedding circuit for polyphase electrical installation - includes OR=gates and AND=gates to monitor individual phase currents and total power consumption with monitoring provided by indicator lamps - Google Patents

Abstract

The circuit is used for a three-phase electrical installation and has an arrangement for balancing the phases, and includes a circuit for each phase, providing a signal when an excess current is detected. The outputs of the measuring circuits are all connected to the inputs of a logic OR-gate via an optical coupler in order to control partial load shedding on the three phases. The outputs are also connected to an AND-gate for each phase. Each AND-gate receives as one input the output of the OR-gate via a delay. The outputs of the AND-gate operate indicator lights (two for each phase) showing the operating conditions at any time. The circuit thus monitors and controls the current taken by individual phases of the supply, as well as the total current taken by all three phases.

Description

 The present invention relates to a load shedder for polyphase electrical installation, with phase balancing device.

 On the current market, there are many marketers whose role is to allow the subscriber to subscribe to an electrical power supply lower than all of his needs: for example, all of the user's needs being 24 KW, the 15 KW subscription associated with load shedding will avoid perpetual tripping of the circuit breaker, but above all will save the subscriber the annual fee difference between the subscriber for a power of 24 KW and that for a power of 15 KW. In addition to its direct financial interest, load shedding is recommended by the Eleetrieité de France, to minimize the subscribed power and limit current draws during heating periods.

 Current load-shedders generally have the following disadvantages or inadequacies. Existing devices are in the form of independent devices for each phase, which detect the variation in intensity either by a toroidal sensor or by a thermal sensor, and which in the event of an overload cut off the supply of the corresponding phase, the operation being carried out according to the "all or nothing" principle. There is no provision for combining the effects obtained on the three phases in association with a partial load shedding of the installation, which would make it possible to distribute or attenuate these effects while meeting the primary purpose, namely the limitation of the instantaneous power con ceimed. In the case of an installation comprising electric heaters , the iodine of action of current load shedders is, for these reasons, detrimental to comfort.

 - Most of the devices offered on the market impose relest times after load shedding varying from 4 to 15 minutes, which is also detrimental to comfort, and it therefore appears desirable to reduce the relest time, while respecting the standards.

 In addition, Electricité de France requires electricians to distribute the power of the installation in a balanced manner over the three phases. This operation is practically not carried out because it requires special equipment (amperometric clamps). The main purpose of the present invention is to add, to a load shedder, a device allowing the installer to easily balance the three phases. In association with this main aim, the invention also proposes a design modification of the load shedder itself, which overcomes the drawbacks mentioned above with regard to current devices, and which makes this load shedder particularly suitable for an installation comprising heating devices electric.

 To this end, the subject of the invention is essentially a load shedder for multi-phase electrical installation, with phase balancing device, comprising for each phase a measurement circuit capable of delivering a signal in the event of detection of an overcurrent, and in which the outputs of all the measurement circuits, on the one hand, are all connected to the inputs of the same logic circuit OR by means of which partial load shedding is controlled over all the phases, and on the other hand, are each connected to a first input of an AND logic circuit associated with a phase and by the means of which the total load shedding of the corresponding phase is controlled, the output of the above-mentioned OR circuit also being connected to a second input of all the AND circuits by means of a delay circuit, provided with neutralization means with a view to balancing the phases, an operation for which light indicators are provided, the number of ten per phase, indicators of a function normal or load shedding, LEDs which are connected to the output of each of the AND logic circuits.

 This load shedder is thus characterized by logic circuits which make it possible to combine the signals coming from the measurement circuits associated with each phase, to obtain the following results -As soon as an overload appears, the device controls a partial load shedding, concerning by example half the power, on all the phases. It is therefore not an "all or nothing" load shedding likely to affect comfort.

-After a certain time, determined by the delay circuit, if an overload remains on a phase, this phase is completely unloaded. Total load shedding therefore always occurs while the phases are already "lightened" by the partial load shedding.

-If the cause of the overload disappears, the total load shedding stops; relesting can be carried out in a time which will be, as a minimum, that defined by the delay circuit, a time which can, without difficulty, be provided for in the order of a minute to favor comfort. second OR logic circuit, one input of which is connected to the output of the first OR circuit, that is to say the one receiving the signals from all the measurement circuits, and of which another input is connected to the output of the delay circuit, at the same time that the shedding also takes place not suddenly, but by passing through an intermediate stage of partial shedding.

-The nntraisation of the delay circuit, combined with the indicator lights associated with each phase, offers the possibility of balancing the phases by taking advantage of the measurement circuits and the logic circuits of the load shedder itself. Neutralization; of the delay circuit perset to have an immediate reaction of the LEDs, which will indicate the normal or overloaded state of each phase. If a phase is overloaded, it is obviously necessary to distribute a part of its loads over one or two non-overloaded phases, and then carry out a new test. Preferably, the means for neutralizing the delay circuit, with a view to balancing the phases, are coupled to a command to remove partial load shedding, to avoid the appearance of any effect which would not be visually controllable using the indicator lights.

 According to a particular embodiment of the invention, the output of each measurement circuit, associated with a phase, is connected to the corresponding input of the first OR logic circuit, as well as to the first input of the corresponding AND logic circuit, by means of a memory associated with an oscillator delivering a signal formed by periodic pulses which trigger the storage at determined times, the oscillator still controlling an additional memory tercalé between the first logic circuit OR and the second OR logic circuit, and means being provided to cause this oscillator to be delivered either a signal with a relatively long period, corresponding at least to the minimum load shedding time imposed, or a signal with a much shorter period with a view to balancing the phases.

In this particular embodiment, the combination of memories (which may be made up of several compartments of a single memory), and of an oscillator delivering periodic pulses, with two possible frequencies, achieves the equivalent of the delay circuit and its means of neutralization (the
high frequency addition of the signal / by the oscillator allowing an almost instantaneous reaction of the LEDs, to operate the balancing). According to another characteristic of the invention, all the logic circuits AND include a third input , which is connected to the oscillator, for example via a transistor, so as to interrupt load shedding for the duration of each pulse of the signal delivered by the oscillator.
This latter arrangement makes it possible to periodically re-establish the current corresponding to the total power requested, and therefore to periodically carry out a new test in order to check whether the cause having caused the load shedding remains, which can avoid certain fluctuations or instabilities.

Anyway, the invention will be better understood & BR <using the description which follows, with reference to the appended schematic drawing representing, by way of nonlimiting example, an embodiment of this load shedder for polyphase electrical installation, with phase balancing device
Figure 1 is a block diagram of a three-phase load shedder according to the invention;
Pigure 2 is a detailed diagram of the circuits of this load shedder;
Figure 3 shows an embodiment of the front of the device;
Figure 4 is a diagram illustrating the operation of the load shedder considered.

 The apparatus shown very diagrammatically in FIG. 7 comprises three identical measurement circuits, generally designated by the reference 1. Each measurement circuit 1 has an intensity sensor 2, crossed by one of the three phases P1 , P2 and P3 of the electrical installation; the output of sensor 2 is connected to the input of an amplifier 3, supplied by an electronic circuit 4 connected between phase P1, P2 or P3 and the neutral conductor N. The gain of each amplifier 3 can be modified by means of a selector 5 associated with several calibration resistors 6, corresponding for example to setpoint currents of 15, 20, 25 and 30 amps. The three selectors 5 are coupled to a common control, which can be implemented in the form of an organ rotary slot 7, operable using a screwdriver (see Figure 3).

The output of each amplifier 3 is connected, via an optical coupler 8, to one of the three inputs of a first OR logic circuit 9, the output of which is connected on the one hand to the input d 'a delay circuit 10, and on the other hand to one of the two inputs of a second logic circuit OR 11. Three logic circuits
AND 12 with two inputs are planned; one input of each AND circuit 12 is connected to the output of one of the three measurement circuits 1, while the other input is connected to the output of the delay circuit 10. This output is also connected to the second input of the second OR circuit 11.

The outputs of the three AND circuits 12 are connected, respectively, to connection points DI, D2 and
D3, for power circuits not shown which control the total load shedding respectively on phases P1, P2 and P3. The output of the second OR circuit It is connected to another connection point D4, for a power circuit controlling partial load shedding on all three phases P1, P2 and P3.

 The outputs of the three AND circuits 12 can also be connected to the inputs of a third OR circuit 13, the output of which is connected to another connection point D5, for a power circuit controlling the complete load shedding of a given device of the installation, in particular of an apparatus which would be supplied simultaneously by several phases.

To allow balancing of the three phases P1,
P2 and P3, the load shedder according to the invention is completed by a button 14 enabling the delay circuit 10 to be neutralized, as well as by two series of three indicator lights, respectively 15 and 16. The output of each logic circuit AND 12 is connected , on the one hand, to one of the three LEDs 15, which are green to indicate normal operation, and on the other hand, to one of the three LEDs 16, which are red to indicate a load shedding of the corresponding phase.

Figure 3 shows a possible arrangement of all these members on the front of the device, which can be embedded in a more complete control panel, in particular the table of a regulation and programming cabinet for an electric heating installation .

Figure 1 also helps to understand the operating principle of the load shedder considered
In normal operation, the button 14 is put on the position "N" (see figure 3) which authorizes the intervention of the delay circuit 10. In the event of overload of one of the phases P1, P2 and P3, detected by the corresponding measurement circuit 7, a logic level "1" is immediately obtained at point A, that is to say at the output of the first OR circuit 9. This signal causes, via the second OR circuit 11, the delivery to connection point D4 of a partial load shedding order on all of the phases P1 P2 and P3.

 After an interval of time, of about one minute, determined by the delay circuit 10, a logic level "1" is also obtained at point B located at the output of this delay circuit. If, despite the partial load shedding provoked previously, an overload remains on one of the phases PI, P2 and F3, the corresponding AND circuit 12 will receive at its inputs two logic levels n 1 ", and it will deliver to the connection point D1, D2 or D3 a total load shedding order for the phase on which the overload occurs, the other two phases remain partially unloaded.

 In the case where the DF connection point is used, the latter issues a complete load shedding order regardless of the phase P1, P2 or P3 on which an overload remains, this thanks to the third OR 13 circuit.

It should be noted that, in all cases, load shedding
total always occurs at a time when the phases are
already lightened. The phase (s) affected by the injury
total tage are indicated by the illumination of the
16 corresponding red lights.

 From the moment the cause of the overload disappears, which caused the load shedding, the total load shedding order at point D1, D2 or D3 immediately stops taking into account the connection of the AND circuits 12. However, due to the intervention of the delay circuit 10, and taking into account the connection of the OR circuit 11, the partial load shedding order, at point D4, will remain for another 1 minute approximately.

 Advantageously, this partial load shedding consists in cutting off half of the power of each phase, divided into two branches, and a switching system, not shown, alternately cuts the first branch and the second branch of each phase if the order of partial load shedding extends, to distribute this load shedding over the entire electrical installation.

 To carry out the phase balancing, after the installation has been completed and its voltage has been applied, the button 14 is placed in position n E "(see FIG. 3), which neutralizes the delay circuit 10 so that the signals at points  and B will be identical at all times, thus an overloaded phase will be signaled immediately by the illumination of the corresponding red light 16.

The electrician can then very easily transfer part of the charges from this phase to another phase, the green light 15 of which is lit, thereby indicating normal operation. The operation can be repeated on a lower caliber 6, chosen by the selector 5, to refine the balancing.

 FIG. 2 shows a possible embodiment of the load-shedding circuits according to the invention, of which FIG. 1 gives the block diagram. In order not to overload this figure 2, the detail of the three identical measurement circuits 1 has only been shown for one of them, namely that associated with the phase PI.

 The intensity sensor of each measuring circuit is constituted by a shunt 2. One of the terminals of the shunt 2 is connected, by means of a capacitor 17 and a variable resistor 8, to the inverted input. of the amplifier 3. The other terminal of the shunt 2 is connected, via a capacitor 19, and the non-inverted input of the amplifier 3.

 The supply circuit 4 of the amplifier 3 supplies a direct voltage, for example of 12 volts, by means of a resistor 20, a diode 21, a Zener diode 22 and a filtering capacitor 23 Between the terminals of this latter capacitor 23 is connected a divider bridge, formed of two resistors 24 and 25 of the same value, the midpoint of which is connected to the non-inverted input of the amplifier 3, thus being thus mounted in alternative n ".

 The calibration resistor 6, chosen using the selector 5, is inserted in the feedback network of the amplifier 3 and thus determines the gain of this amplifier).

 The output of the amplifier 3 aliiente, via a Zener diode 26, a photodiode 27 belonging to the optical coupler 8 0n thus supplies the photodiode 26 with a voltage equal to the difference between the threshold of the Zener diode 26, by example 9 volts, and the rest point of the amplifier 3, adjusted to 6 volts by the divider bridge 24-25 in the case of a supply circuit 4 delivering a direct voltage of 12 volts. A resistor 28, mounted in series with the photodiode 27, fixes the potentate at rest and avoids picking up parasites.

 The optical coupler 8 also takes a phototransistor 29, mounted in parallel with a capacitor 30 which is associated with a load resistor 31.

 In the measurement circuit 1, each passage of the crest of the sinusoid above the threshold defined by the Zener diode 26 causes the photodiode 27 to be supplied and, consequently, the phototransistor 29 illuminated by this photodiode. The photo transistor 29 then short-circuits the capacitor 30.

The load resistor 31 is chosen so as to give a time constant much greater than the period of the pulses delivered by the measurement circuit 1, which is the period of the sector to which the three phases P1, P2 and P3 are connected. Consequently, as long as the measurement circuit 1 delivers pulses, the capacitor 30 cannot be recharged.

 This capacitor 30 therefore converts the presence or absence of periodic pulses, delivered by the measurement circuit 1, into a continuous signal which represents a logic level O 0 "or 1". The signals thus obtained, corresponding to the three phases F1, P2 and F3, are brought to the inputs of three of the compartments of a quadruple memory 32, the logic levels stored in memory being designated by Q1, Q2, Q3 and Q4.

The outputs of the first three compartments of memory 32 are connected to the three inputs of an AND gate 9 'which performs the equivalent of the first logic circuit
OR 2 of FIG. 1, taking into account the complementarity of the logic levels between FIGS. 1 and 2. The same outputs of the memory 32 are also connected, respectively, to one of the inputs of three OR gates 12 'to three inputs, which provide the equivalent of the three logic circuits EX 12 in FIG. 1. The outputs of the three OR gates 12 'are connected, as already described above, to connection points D1, D2, D3 and possibly
D5 (via an EX gate 13 'which is equivalent to the logic circuit OR 13), as well as the three green LEDs 15 and the three red LEDs 16; the latter can be produced in the form of light-emitting diodes, connected in series with resistors, respectively 33 and 34.

 The output of the OR gate 9 is connected to two of the inputs of an AND gate 11 'with three inputs, which performs the equivalent of the logic circuit OR II of FIG. 1.

This output is also connected to the input of the fourth compartment of the memory 32, by means of a delay circuit constituted by a resistor 35 and a capacitor 36. The output of the last compartment of the memory 32 is connected to the third entrance of door Elt 11 ', as well as the second entrance of each of the three doors OR 12'.

With memory 32 is associated an "asymmetrical" oscillator 3?, Providing a signal T consisting of a level "1" interrupted periodically by short pulses of level n on, two resistors 38 and 39 defining the ratio between the duration of these pulses and the oscillation period. This oscillation period is also determined by switching on one or the other of two capacitors 40 and 41, of very different capacities, the selection of the capacitor 40 or 41 being obtained by a change-over contact 14aligned with button 14 which makes it possible to select normal operation or phase balancing (positions respectively
Do not). It should be noted that this button 14 is also linked to a second contact 14b interposed between the output of the AND gate 11 ′ and the connection point D4 for controlling the partial load shedding on all three phases.

The output of oscillator 37, delivering the signal
T, is connected not only to memory 32, but also, via a resistor 42, to the base of a transistor 43 connected in series with another resistor 44; transistor 43, constituting an inverter, is connected to the third input of each of the OR gates 12 '.

 In normal operation of the load shedder, the button 14 switches on the capacitor 40, the capacity of which is chosen so as to obtain a signal T whose period is approximately 1 minute, and it also provides the link between the AND gate 11 'and point D4 (this state of the circuits being that shown in FIG. 2).

 If none of the three phases P1, P2 and P3 is overloaded, all the measurement circuits 1, associated with the capacitors 30, deliver signals El, E2 and E3 of logic level "1" "to the corresponding inputs of the memory 32. The contents Q1, Q2 and Q3 of the first three compartments of memory 32 remain at level "1".

 As soon as the intensity I1, I2 or I3 of one of the phases exceeds a threshold S (see the diagram in FIG. 4), the signal E1, E2 or E3 delivered by the corresponding measurement circuit 1 and the associated capacitor 30 goes to logic level "O". However, the content Q1, Q2 or Q3 of the corresponding compartment of the memory 3t changes to the state "O" only at the first instant t when this memory 32 receives a pulse of the signal T coming from the oscillator 37. From this instant ti , the logic gates 9 'and 11' reveal, at point D4, a logic level "O" which constitutes the order of partial load shedding.

 Taking into account the intervention of the delay circuit 55-36, which introduces a delay of the order of 2 seconds for example, the signal E4 present at the input of the fourth compartment of the memory 32 goes to level "O" after the end of pulse t1, so that the content Q4 of the latter compartment reaches state "O" only at the next pulse t2.

 If the overload remains at this instant t2 (which is the case for the first phase, in the operating example illustrated by the diagram in FIG. 4), the logic gate 12 ′ corresponding to the phase concerned intervenes to reveal, at the point such as D1, a logic level no "which constitutes the total load shedding order of the phase.

The transistor 43 is switched by the pulses of the periodic signal T, which has the effect of interrupting the load shedding during these pulses, therefore of temporarily restoring all the power of the phase (what the diagram shows, at time t3, for the first phase - note that the signal at point D1 returns to the level
1 "during this pulse t3).

 From the moment (t4 in the case of the first phase misery) when the overload is no longer observed, the content Q1, Q2 or Q3 of memory 32 returns to state 1 ", and the logic circuits do immediately stop the total load shedding order for the phase concerned. On the other hand, the intervention of the delay circuit 35-36 has the effect of allowing the content 1 of memory 32 to return to the state "1 only from the next pulse (t5 in the example considered here). Partial load shedding is therefore maintained for an additional time interval.

 The diagram in FIG. 4 also illustrates the combination, by the logic circuits, of the logic signals resulting from overloads on more than one phase (assuming that an overload, appearing on the second phase, is memorized at the instant of l impulse t4).

 The description which has just been made shows that the circuits of FIG. 4 do indeed make it possible to obtain the operation the principle of which has been described with reference to FIG. 1 (whose delay circuit, symbolized by block 10, results in made of the combination of memory 32 and oscillator 37 which provides a "time base").

 In order to carry out phase balancing, the button 14 is moved to switch on the condensate tower 41, which allows the oscillator 37 to deliver much closer pulses (for example: one pulse per second), to that the LEDs 15 and 16 can give an almost instantaneous indication (the operation being carried out as described previously, but at a much higher speed). By its contact 14b, the button 14 also cuts the connection with the connection point D4, so that balancing can take place by simply distinguishing between the overloaded and non-overloaded phases, directly identifiable by the indicator lights provided, and by excluding any partial load shedding from all the phases.

 It goes without saying that the invention is not limited to the sole embodiment of this load shedder for polyphase electrical installation, with phase balancing device, which has been described above by way of example; on the contrary, it embraces all variants comprising provisions constituting equivalents of the elements described.

Claims (8)

-BENDENDICATIONS  1.- Load shedder for polyphase electrical installation, with phase balancing device, comprising for each phase a measuring circuit capable of delivering a signal in the event of detection of an overcurrent, characterized in that the outputs of all the circuits on the one hand, are all connected to the inputs of the same OR logic circuit (9) by means of which partial load shedding is controlled over all the phases (P1, P2, P3) , and on the other hand, are each connected to a first input of an AND logic circuit (12) associated with a phase (P1, P2, P3) and by means of which the total load shedding of the corresponding phase is controlled, the output of the above-mentioned OR circuit (9) also being connected to a second input of all the circuits AND by means of a delay circuit (10), provided with neutralization means (14) with a view to balancing the phases (P1, P2, P3), an operation for which light indicators are also provided ( 15w, 16), two in number per phase, indicators of normal operation or load shedding, indicators which are connected to the output of each of the AND logic circuits (12).  2.- Load shedder according to claim 1caractErisé in that there is provided a second OR logic circuit (11), one input of which is connected to the output of the first OR circuit (9), that is to say the one receiving the signals from all the measurement circuits (1), and another input of which is connected to the output of the delay circuit (10).  3. Load shedding device according to claim 2, characterized in that the outputs of all the AND logic circuits (12) are connected to the inputs of a third OR logic circuit (13), by means of which the complete load shedding is controlled d 'a given device of the installation, in particular a device powered simultaneously by several phases.  4.-Load shedder according to any one of claims 7 to 3, characterized in that the neutralization means (14) of the delay circuit (10), with a view to balancing the phases (PV, P2, P3) , are coupled to a command (14b) for removing partial load shedding.  5. Load shedding device according to claim 2 or 3, characterized in that the output of each measurement circuit (1), associated with a phase (P1, P2, P3), and connected to the corresponding input of the first circuit OR logic (9), as well as at the first input of the corresponding AND logic circuit (12), via a memory (32) associated with an oscillator (37) delivering a signal (T) formed by pulses periodicals which trigger the storage at determined times, the oscillator (37) further countering an additional memory interposed between the first OR logic circuit (9) and the second OR logic circuit (11), and means (14a, 40 , 41) being provided to cause this oscillator (37) to deliver either a signal (T) of relatively long period, corresponding at least to the minimum load shedding time imposed, or a signal (T) of much shorter period, in order to phase balancing (P1, P2, P3).  6. * Load shedder as claimed in claim 5, characterized in that the output of the first OR circuit (9) is linked to the input of the additional memory (32) via a delay circuit (35,36 ).  7. Load shedding device according to claim 5 or 6, characterized in that the means allowing the oscillator (37) to deliver a signal (e) of long or short period consist of two capacitors (40,41), of capacities very different, one or the other is switched on by a change-over contact (14a).  8. Load shedding device according to any one of claims 5 to 7, characterized in that all the AND logic circuits (12) comprise a third input, which is connected to the oscillator (37), for example by means of d a transistor (43), so as to interrupt load shedding for the duration of each pulse of the signal (T) delivered by the oscillator (37).