FR2488007A1 - Arbitration method for units of multiprocessing system - has accelerated priority determn. when claimed by one unit only - Google Patents

Abstract

Each processor in a system comprising p levels with n processing units per level is equipped with an arbitration circuit which incorporates two conventional elementary arbiters, each having a register with eight D flip-flops and an eight-input four-output 14OM. Priorities are assigned in accordance with a main cycle in a definite order to each level, and distributed in accordance with longer sec. cycles to each processor. When no other unit claims priority, the determn. is accelerated by sending to the input of an AND gate the request stages of all units at the same level and all other levels. The output of the gate is applied to the bus utilisation authorisation input of the unit concerned via an OR gate and a D flip-flop. Priorities can be determined easily and rapidly even for a large number of processors.

Description

 The present invention relates to a method for accelerated arbitration of several processing units as well as to an arbitration device for a multiprocessor system.

 We know from the article on pages 154 to 158 of the April 1978 issue of the journal "Computer Design" an arbitration process and an arbitration device for a multiprocessor system comprising several identical processing units all connected to the same bus. This known arbitrator, of the synchronous type, makes it possible to establish a rotating priority between the different processing units so that none of them monopolizes the bus, and so that the processing carried out by the multiprocessor system is as rapid as possible. The known arbitrator essentially comprises a read-only memory in which are programmed all the possible configurations of bus reservation requests and of corresponding states.

 This known device requires a large number of connecting wires between the arbitrator device and the different processing units, which can be annoying when the number of processing units is high.

 In addition, the size of the ROM used in the known arbitrator is a function of the number of processing units cooperating with it. If the number of processing units is small, the capacity of the read-only memory necessary to carry out the arbitrator is correlatively low, and the arbitrator is therefore inexpensive and easy to carry out. On the other hand, if the number of processing units is high, it is necessary to use several large capacity memories, and the realization of the arbitrator becomes complex and expensive.

 The present invention relates to a method of arbitration of several processing units allowing a simple and rapid determination of priorities, even for a large number of processing units, and making it possible to accelerate this determination when a single unit claims the priority.

 The present invention also relates to an arbitration device which does not have the drawbacks of the known device, which is easy to produce and inexpensive.

 The arbitration method according to the present invention consists, after having divided the processing units into several groups or "levels" comprising, preferably, the same number of processing units each, to reserve for each of these levels a single or several priorities which are assigned during a main cycle, to reserve for each of the processing units within each level one or more priorities which are assigned according to secondary cycles, the duration of a secondary cycle being equal to that of several main cycles, and to be determined for each processing unit having issued a bus reservation request, first, the instant when priority returns to the level of which it is a part, and second, l 'the instant when priority returns to this processing unit inside this level, and If a single processing unit claims priority, it is granted immediately without initiating cycles.

 According to a preferred aspect of the process of the present invention, there is reserved for the main cycle only one priority at each of the levels, and this according to a predetermined order fixed in advance, and we reserve, for the secondary cycles, in each level, only one priority for each of the processing units, and this in another determined order, fixed in advance.

 According to another aspect of the method of the invention, the processing units are distributed in each level or in some of them in several sub-levels, each of the levels is reserved for one or more priorities, which are assigned during a main cycle, we reserve for each of the sub-levels one or more priorities which are assigned during secondary cycles, and we reserve for each of the processing units within each sub-level a single or several priorities which are assigned during tertiary cycles, the duration of a secondary cycle being equal to that of several main cycles, and the duration of a tertiary cycle being equal to that of several secondary cycles, and it is determined for each processing unit, first the instant when the priority returns to the level of which it is a part, secondly the instant when the priority returns to the sub-level of which it is a part, and thirdly the instant when the prior ity returns to him inside his sub-level.

 The arbitration device according to the present invention, and applied to pn processing units divided into g levels each comprising n processing units, comprises, in each processing unit, an arbitration unit, the arbitration units being connected , in a m dismal level, to a common link for requesting allocation of level priority, links to request for priority allocation connecting each time an output of request for allocation of an arbitration unit to Entries for taking into account the request for priority allocation of all the other arbitration units of the same level, each common link for requests for assigning priority of level being linked to a corresponding entry for taking into account the request for level priority assignment of each of all arbitration units.

According to a characteristic of the preferred embodiment of the invention, all the arbitration units are identical and each comprise: a first elementary arbitrator known per se, the inputs of which are linked to the corresponding inputs for taking into account the request for allocation of priority of the arbitration unit under consideration, and whose output, corresponding to the rank of the elementary arbitrator under consideration, is connected to a first input of a first AND circuit with two inputs; a second elementary arbitrator whose inputs are linked to the corresponding inputs for taking into account requests for allocation of priority of level of the arbitration unit considered, and whose output, corresponding to the rank of the level in which is located the arbitration unit considered, is connected to the second input of said first circuit
AND; a first OR circuit whose number of inputs corresponds to the number of arbitration units of the level considered, each of the inputs of this OR circuit being connected to an input for taking into account the request for priority allocation of the unit arbitration considered, and the output of this OR circuit being connected to the corresponding input for taking into account the request for allocation of level priority corresponding to the rank of the level of the arbitration unit considered; and an acceleration circuit comprising a second AND circuit whose number of inputs is equal to the sum of the number of processing units in the level considered and the number of levels minus one, a first input of this AND circuit being directly connected to the priority allocation request output of the processing unit considered, the other inputs of this second AND circuit being each time connected via a logic inverter on the one hand to the request outputs d 'priority allocation of all other processing units of the same level as that of the unit under consideration, and on the other hand to the common links of requests for allocation of priority of level of all the levels other than that considered; this acceleration circuit also comprising a second OR circuit with two inputs, one input of which is connected to the output of said first circuit
AND with two inputs and the other input of which is connected to the output of said second AND circuit, the output of this second OR circuit being connected via a flip-flop of type D to the authorization input of use of bus of the arbitration unit considered.

 According to another characteristic of the device of the invention, to standardize printed circuit cards each comprising a processing unit with its arbitration unit, as well as a first connector part secured to these cards and cooperating by plugging in with a second connector part secured to the chassis receiving all the cards in the system, the first part of the connector of each card is connected, and in the same way for all the cards: the output of request for allocation of priority; the output of said first OR circuit; all exits of the first elementary referee; all the outings of the second elementary referee; the two inputs of said first AND circuit and each time via a logic inverter all the inputs, except the first, of said second AND circuit; and one connects by wiring, in the second connector part: the output of request for allocation of priority to the corresponding input input; the output of the first OR circuit to the corresponding input for taking into account the request for allocation of level priority; the first input of the first AND circuit to the corresponding output of the first elementary arbiter; the second input of the first circuit AND to the corresponding output of the second elementary arbitrator; and the terminals of the second connector part are connected by wiring on the one hand to all the inputs for taking into account the request for priority allocation except that corresponding to the processing unit considered, and on the other hand to all entries to take into account the request for allocation of level priority except that corresponding to the processing unit considered.

The present invention will be better understood on reading the detailed description of an embodiment taken as a nonlimiting example and illustrated by the appended drawing, in which - Figure I is a block diagram of a multiprocessor system
comprising an arbitration device in accordance with this
invention, and, - Figure 2 is a diagram of an arbitration unit of the device
Figure 1.

 The multiprocessor system partially represented in FIG. 1 comprises p.n identical processing units distributed in p levels, each level comprising n processing units.

Preferably, if the number (pn) is a perfect square, we choose p 5 n, and otherwise, we choose 2 as close as possible to n, p can be greater or less than n. In the case shown in FIG. 1, the processing units are referenced UT 1.1 to UT for the first level, UT2.1 to UT2 for the second level, and so on up to the rank level p for which the units of treatment are referenced UT I to
p. 1 PN UT, the ranks l to p being respectively referenced Nl to Np. Each of the processing units UTl.l to UTp. n includes an individual arbitration circuit, respectively referenced CAl.l to CAp. not . All processing units UT ll to UTp. n are connected to a common bus (not shown).

Each of the individual CAI I to CA arbitration circuits
pn includes: an output SB of bus request or individual priority allocation request, an output SN of priority allocation request at the level of which it is a part, several EB inputs for taking into account priority allocation request individual and several inputs E to take account of allocation requests
level priority n.

 Each input E B of an individual arbitration circuit is connected to a corresponding output SB of all the other individual arbitration circuits of the same level. Consequently, in the present case, each individual arbitration circuit comprises (n-1) input EB, and its output SB is connected to an input EB of all the other individual circuits of the same level. In addition, as will be explained below with reference to FIG. 2, the bus request output of each individual arbitration circuit must be connected to its own input for taking into account the bus request. be done internally in each of the individual circuits, conne this is the case for Figure 1 in which this connection has not been shown. For the purpose of interchangeability of the individual circuit cards, as explained below with reference to FIG. 2, this connection can also be made at the level of the connectors of the cards, and in this case each individual circuit has n EB inputs of which l one is connected externally to its own output SB.

All the outputs SN of the individual arbitration circuits of the same level are connected via an OR circuit, for example a wired OR (not shown), to a common level link referenced LNI to LNp for the levels NI to Np respectively. Each of the EN inputs of each of the individual circuits is connected to a link of a different level. Each individual arbitration circuit therefore comprises in this case p inputs E
not
We will now describe with reference to FIG. 2 a preferred embodiment of an individual arbitration circuit, namely the circuit CAl.m ', that is to say the circuit of rank m in the level of rank 1 In the example shown in Figure 2, Q = 2 and m = 3, and the circuit shown is the circuit Cas 3.

By hypothesis (p.n) = 16, and we preferably choose p = n s 4.

However, it is understood that the invention applies to a multiprocessor system having any number (p.n) of processing units. This number can even be prime, the levels NI to Np then having different numbers of processing units.

 The circuit CA2 3 essentially comprises two elementary arbitrators 1, 2 respectively, of a type known per se from the above-mentioned article in "Computer Design". These elementary arbitrators each include a register with eight flip-flops of type D, referenced 3, 4 respectively, the eight outputs of which are connected to the eight addressing inputs of a # e read-only memory with four outputs referenced 5, 6 respectively. first four inputs of registers 3 and 4 are connected to connectors, referenced 7 and 8 respectively, integral with the printed circuit card 9 supporting the components of the arbitration circuit CA, and where appropriate the corresponding processing unit (not represented and which would be referenced UT2.3) The four outputs of the read-only memories 5 and 6 are connected, on the one hand to connectors respectively referenced 10 and 11, and on the other hand to the other four inputs of the registers 3 and 4 respectively.

 The first four inputs of register 3 are also connected to the four inputs of a circuit 12 with an OR function, the output of which is connected to a connector 13 secured to the card 9.

The circuit CA2 3 also includes a gate 14 with AND function and two inputs. The two inputs of the AND gate 14 are connected to a connector 15, and its output is connected to a first input of a gate 16 with OR function, the output of which is connected to a flip-flop 17 of type D. The output of the flip-flop 17 is connected to a terminal 17a, itself connected, not shown, to the bus use authorization input of the processing unit UTZ 3
The clock signal inputs of flip-flops 3 and 4 are connected to terminals 18 and 19 respectively, themselves connected together, in a manner not shown, and to an output of a suitable clock signal generator (not shown ). The clock signal input of flip-flop 17 is connected to a terminal 20, itself connected to said output of the clock signal generator. The terminals such as terminals 18, 19 and 20 of all the individual arbitration circuits are connected together to the same so-called output of the clock signal generator.

 The output (not shown) of bus request of the processing unit UT2.3 is connected to a terminal 21 disposed on the card 9 and connected to a connector 22 secured to this same card 9 (in the case where the components of the processing unit UT2 3 are mounted on the card 9. Otherwise, the terminal 21 and the connector 22 are deleted. Said bus request output of the unit UT2 3 is also connected to a first input of an AND gate 21a with seven inputs, the output of which is connected to the second input of the OR gate 16. It is also mounted on the card 9 a connector 7a with six terminals which are each connected to a corresponding input of the AND gate 21a via a logic inverter, these six logic inverters being able to be integrated in the gate 21a.

 Of course, for reasons of simplicity of construction, the connectors 7a, 7, 8, 10, 11, 13, 15 and 22 can be combined into a single multiple connector.

 The eight connectors 7a, 7, 8, 10, 11, 13, 15 and 22, integral with the card 9, cooperate with corresponding complementary connectors fixed on the frame or chassis (not shown) supporting the other elements of the multiprocessor system of which part of the Ca2.3 circuit. These corresponding complementary connectors are respectively referenced 23a and 23 to 29, and can also be combined into a single multiple connector.

 For the convenience of the description and explanations, it is assumed that the first four inputs of registers 3 and 4 and that the four outputs of memories 5 and 6 correspond, in the order drawn, from top to bottom, to the rank of circuits d arbitration within levels, or at the rank of levels, as the case may be.

Thus, the four pins of the connector 23, which are connected, on the side of the card 9, via the connector 7, to the first four inputs of the register 3, are connected externally to the card 9, to the outputs Sg of the other circuits CA2.1 to CA2.4 respecti-CA2.4 vement. Only the link 30 to the output SB of the circuit CA2.1 to CA2.3 has been shown: this output SB is in fact the external connection pin of the connector 29. Because only the circuit CA2 3 has been shown, there is n has not shown the connections of the output SB of the circuit Cl, 3 to the inputs EB3 of the other circuits c4 1 CA2 2 and CA2 4, nor the connections of the outputs 5B of these other circuits to the terminals EB1, EB2 and EB4 respectively.

The circuit CA2 3 being in level 2, its output SN, which is in fact the external connection pin of the connector 27, is connected by the link LN2 to its input EN2,. The input EN2 is in fact the second pin external connection of connector 24, and this pin is connected, via connector 8, to the second input of register 4. The other connections of SN and EN1,
EN3 and EN4 at the corresponding inputs and outputs of all the other arbitration circuits were also not represented.

 The first three external connection pins of connector 23a are respectively connected to terminals EB1, EB2, and EB4.

The other three external connection pins of connector 23a are respectively connected to terminals EN1, EN3 and EN4.

The four outputs of the memory 5 or individual authorization memory are connected via the connector 10 to the four external connection pins of the connector 25, which constitute four individual authorization output terminals, respectively referenced 5AI1 to SAI4. The four outputs of the memory 6 or level authorization memory are connected, via the connector 11 to the four external connection pins of the connector 26, which constitute four level authorization output terminals, respectively referenced SAN1 at SAIN4. The two external connection pins of connector 28, which constitute the individual authorization and level authorization input terminals, are respectively referenced E AI and EAN. Given that the circuit represented in FIG. 2 is the third circuit from the second level, the SAI3 pin of the conductor 25 is connected by the connection wire 31 to the pin E AI of the connector 28, and the SAN2 pin from the connector 26 to the pin is connected by a connection wire 32
EAN of connector 28.

 We will now explain the operation of the device described above, with reference to the case where p = n = 4. In this device, the memories 5 and 6 of the elementary arbitrators 1 and 2 of each of the individual arbitration circuits are programmed to analogous to that indicated in the above article from the journal "Computer Design". However, unlike the known method, and as explained in more detail below, in accordance with the method of the present invention, the allocation of priorities is carried out. first according to a main cycle during which the priority is distributed according to a determined order, preferably only once during a cycle, at each level by making the request, and then, according to secondary cycles for each of the levels, the priority being distributed, for each of the levels, in a determined order, preferably only once during a cycle, to each of the processing units of the same level which requests it. In addition, it should be noted that the determination of the present and future states of each of the processing units or of each of the levels can be done in different ways. In the simplest case, only two states are considered, namely: master of the bus or not. One can also envisage, as is the case for the embodiment shown in FIG. 2, four different states, namely: at rest, bus master, in reserve (that is to say, having to be master of the bus during the main or subsequent secondary cycle) and on hold (that is, before being master of the bus during one of the main or secondary cycles following said subsequent cycle). it is also possible to provide either three states (by deleting the "pending" state) or five or more states (by ordering the "pending" state (s)).

 For the reasoning which follows, we will first of all ignore the role of gate 21a, as if its output was not connected to the second input of the OR circuit 16.

 As soon as a bus allocation request is sent by a processing unit, for example the processing unit UT2 3, in the form of a logic "1", this signal appears on the output SB of this processing unit . The output SB of the circuit Cl, 3 of the unit UT2 3 being connected to the inputs Egî of all the arbitration circuits of the processing units of level 2, each of these circuits knows, thanks to the corresponding addressing of its memory 5 , that the circuit c4 3 has requested the allocation of the bus, and that as soon as an active edge of the clock signal is applied to the terminals 18 and 19.

In addition, a "1" appears at the output of the OU 12 of the circuit CA2 3, and is transmitted to the inputs EN2 of all the individual arbitration circuits. As soon as said active edge of the clock signal is applied to the terminals 18 and 19, each of the individual arbitration circuits, and in particular those of the levels NI, N3 and N4, knows, thanks to the corresponding addressing of its memory 6, that a request for allocation of the bus emanates from at least one of the circuits of level N2. Consequently, if no other request is emitted by the individual circuits of abitration of the levels NI, N3 and N4 , the memory 6 of the circuit Cl, 3 produces a "1" on the output
In addition, if in level N2 no other processing unit issues a request, the memory 5 of the circuit C1, 3 produces a "1" on the output SATI3 The AND gate 14 therefore receives a "1" on each of its two inputs, and, produces a 1 on its output. As soon as a second active edge of the clock signal is applied to terminal 20 of flip-flop 17, a "1" appears on terminal 17a, and the processing unit UT, 3 is authorized to use the bus to which it is connected.

 We will now examine what happens in the same case (only the processing unit UT23 requests priority) taking account of the gate 21a. As soon as the processing unit UT2 3 requests priority, that is to say as soon as a "1" appears on terminal 21, door 21a has a "1" on its first input, and also " 1 "on its other six entries. Indeed, since no other processing unit requires the use of the bus, "O" are present on the terminals EBI, EB2, EB4 and ENî, EN3 # EN4, therefore "1" are present at the outputs of the inverters connected to the other six entrances to gate 21a. Consequently, a "1" appears at the exit of the gate 21a and therefore at the exit of the gate 16.As soon as a first active edge of the clock signal is produced, the flip-flop 17, in particular, is activated, and a "1" appears on its output terminal 17a and the processing unit UT is immediately authorized to use the bus. In addition to this, said first active edge of the clock signal activates registers 3 and 4, and memories 5 and 6 are therefore addressed as explained above and produce a "1" on outputs S and SAI3 and SAN3, so a "1" at the exit of 14 and 16.

The second active edge of the clock signal activates in particular the flip-flop 17 and a "1" appears on its output 17a, this "1" confirming the "1" due to the first active edge of the clock signal and appeared previously on the terminal 17a.

Of course, if another processing unit requests the use of the bus between the first and second active edges of the clock signal, the second active edge modifies the addressing of the memories of the corresponding individual arbitration circuits, and a " O "appears on SA output B. Thus, the UT 3 unit will have carried out a
2.3 elementary operation between the first and the second active edges of the clock signal thanks to the "1" produced by the gate 21a, and another elementary operation between the second and the third active edges of this clock signal thanks to the "1 "produced by memory 5 when it is addressed by the first active edge, then between the third and fourth active edges, said other processing unit performs an elementary operation. We therefore see that the circuit comprising AND gate 21a is a circuit d acceleration of priority allocation making it possible to advance by one period of the clock signal the start of the processing carried out by the processing unit in question, without waiting for the second active edge of this clock signal.

 In all other cases, that is to say when several processing units simultaneously request the use of the bus, an "O" is present at the output of the AND gate 21a, and it is therefore inactive.

Consequently, in the following explanations dealing with these other cases, door 21a will not be taken into account.

If, in level N2 only, two or more processing units simultaneously request the use of the bus, only the individual authorization memory of the processing unit with the highest priority at this time issues a "1" on the output d 'corresponding individual authorization. On the other hand, all the level authorization memories of the arbitration circuits of level N2 produce a "1" on the output SAN2 of each of these circuits. Consequently, only the AND gate of the individual arbitration circuit of the highest priority processing unit receives a "1" on each of its two inputs, and only this processing unit receives authorization to use the bus. As soon as this processing unit has performed an elementary operation (reading or writing a word for example), priority passes to the next processing unit in order of priority and having issued a request. This process continues for all level units
N2 having issued a request, and each of these units performs an elementary operation. If at the end of this first priority allocation cycle, one or more processing units still have other elementary operations to perform, other priority allocation cycles take place, until requests are exhausted.

 If, at a given time, during a cycle for assigning priority to the processing units of level N2, processing units belonging to other levels issue requests for allocation of the bus, the priority is withdrawn from the level 2 immediately after completion of the elementary operation carried out at the given instant.

Indeed, a "1" appears on each of the common level links LN1, LN3 or LN4 corresponding to the levels in which these requests occurred, and these "1" are found on the corresponding inputs EN1, EN3 or EN4 of all individual arbitration circuits, and in particular those of level N2. Level authorization memories of individual level circuits
N2 therefore receive a new addressing configuration from the application, just after said given instant, of an active edge of the clock signal on the terminals such as 19. This new configuration produces in particular a "0" on the outputs SAN2 of all individual circuits at level N2, which removes priority at level N2. Furthermore, the level authorization memories of the individual circuits of the level having issued at least one request and having the highest priority after the level N2, for example the level N3, then produce a "1" on the corresponding outputs SAN3. In this level N3, the highest priority processing unit receives authorization to use the bus for a single elementary operation. Priority immediately passes to the next level in order of priority and having issued a request, and the processing unit with the highest priority at this level also receives authorization to use the bus for a single elementary operation.

As soon as all the levels which have issued requests have received priority so that their highest priority processing unit can perform an elementary operation * i.e. at the end of a first main cycle, priority returns to the level N2, and a second main cycle begins. During this second main cycle, priority is assigned once to each of the levels where at least one request remains, and in each of the levels, priority is assigned to the next processing unit, in order of priorities within the level considered, that coming from having priority during the first main cycle.

After the completion of the second main cycle, other main cycles take place as long as requests remain, these main cycles may be different, if there are no more requests in one or more of the levels after completion of 'a main cycle, and / or if requests appear in a level where there was none previously. For each level where several requests arise, priority is assigned according to a secondary cycle. If n processing units of the same given level require the use of the bus, it takes n main cycles to complete a single secondary cycle of this given level. Reading the explanations above, and knowing the article of " Computer Design "those skilled in the art can very easily program memories such as memories 5 and 6.

 In the case of the preferred embodiment of FIG. 2, all the individual arbitration circuits CAl.l to CAp.n are identical to the circuit CA2.3 and all their memories are programmed exactly like memories 5 and 6 respectively. Only the connections LN2, 30, 31 and 32, and those of the connector 23a, external to the printed circuit boards comprising the components of the individual circuits, are made specifically for each processing unit. Consequently, the printed circuit boards comprising the individual arbitration circuits and, where appropriate, the corresponding processing units, are all interchangeable, which facilitates the maintenance of the multi-processor system according to the invention.

 The distribution of processing units into several levels or even sub-levels makes it possible to have individual arbitration circuits which are relatively simple and easy to implement, even when the number of processing units of the multiprocessor system is very high. Read only memories such as memories 5 and 6 are very easy to program due to their relatively low capacity: in the case, which can be considered very complex, of a multiprocessor system with sixteen processing units, memories 5 and 6 are identical and are of the very common type with 256 x 4 binary elements.

 In the context of the invention, it is also possible to modify the order of priorities at any time, for example by replacing one or more of the read-only memories of the individual arbitration circuits with other memories programmed differently. These other memories can be switched by any suitable device controlled manually or by the multiprocessor system itself. it is also possible to use random access memories instead of read only memories, the content of these random access memories being modified by known suitable means.

 On the other hand, the levels can be subdivided into sub-levels, the elementary referee 2 becoming the sub-level referee, and an additional elementary referee being arranged in each individual arbitration circuit, the connection of this additional referee being similar to that of arbitrator 2, its input being connected to the output of another OR gate whose inputs would be in parallel with the inputs of elementary arbitrator 2, and the appropriate output of this arbitrator being connected to a third input of the gate AND 14 provided accordingly.

 Finally, it is understood that the invention is not limited to application to a multiprocessor system but can be applied to any system in which it is necessary to arbitrate between several subsets using a common communication channel.

Claims (3)

 1. Method of accelerated arbitration of several processing units of a multiprocessor system according to which, after having divided the processing units into several groups or "levels" comprising, preferably, the same number of processing units each, one reserves for each of these levels one or more priorities which are assigned during a main cycle, each processing unit within each level reserves one or more priorities which are assigned according to secondary cycles, the duration of a secondary cycle being equal to that of several main cycles, and it is determined, for each processing unit having issued a bus reservation request, first, the instant when priority returns to the level at which it is a part, and secondly, the instant when priority returns to this processing unit within this level, characterized in that if only one processing unit claims priority, it is grant it immediately without starting cycles.  2. Arbitration device for the implementation of the method according to claim 1 and applied to pn processing units (UT1 # 1 .. UT) divided into levels (N1 .. N) each comprising n processing units, this device comprising, in each processing unit, an arbitration unit (CA1 1 - CA), the arbitration units being connected, in the same level, to a common link for requesting allocation of level priority (LN1 .. LN of the priority allocation request links connecting each time a priority allocation request (SB) output of an arbitration unit to inputs for taking into account the priority allocation request (EB) of all the other arbitration units of the same level, each common link for request for allocation of level priority being linked to a corresponding input for taking into account the request for allocation of level priority (EN1 .. ENp) of each of all arbitration units, characterized in that all the arbitration units are identical and each comprise - :: a first elementary arbitrator (1) known per se, the entr-eeX of which are linked to the corresponding entries (EB) for taking into account the request for allocation of unit priority of arbitration considered, and whose output (SA), corresponding to the rank of the elementary arbitrator considered, is connected to a first input of a first AND circuit with two inputs (14); a second elementary arbitrator (2) whose inputs are linked to the corresponding inputs (EN) for taking into account the request for allocation of priority of level of the arbitration unit considered, and whose output (SAN), corresponding to the rank of the level in which the arbitration unit considered is located, is connected to the second input of said first AND circuit, a first OR circuit (12) whose number of inputs corresponds to the number of arbitration units of the level considered, each of the inputs of this OR circuit being connected to an input for taking into account the request for priority allocation of the arbitration unit considered, and the output (SN) of this OR circuit being connected to the input correspondent for taking into account the request for allocation of level priority corresponding to the rank of the level of the arbitration unit considered; and an acceleration circuit comprising: a second AND circuit (21) whose number of inputs is equal to the sum of the number of processing units in the level considered and the number of levels minus one, a first input of this circuit AND being directly connected to the output (21) of request for priority allocation of the processing unit considered, the other inputs of this second AND circuit being each time connected via a logic inverter of a part to the priority allocation request outputs of all the other processing units of the same level as that of the unit under consideration, and on the other hand to the common level priority allocation request links of all the other levels than that considered; this acceleration circuit also comprising a second circuit OR (16) with two inputs, one input of which is connected to the output of said first AND circuit with two inputs, and the other input of which is connected with the output of said second AND circuit, the output of this second OR circuit being connected by l 'via a D-type flip-flop (17) at the bus authorization authorization entry (17a) of the arbitration unit under consideration.  3. Device according to claim 2, characterized in that to standardize the printed circuit cards each comprising a processing unit with its arbitration unit, as well as a first connector part secured to these cards and cooperating by plugging in with a second connector part secured to the chassis receiving all the cards of the system, the first part of the connector of each card is connected, and in the same way for all the cards: the output of request for allocation of priority; the output of said first OR circuit; all outputs  the first elementary arbitrator; all the outings of the second elementary referee; the two inputs of said first AND circuit and each time through a logic inverter all the inputs, except the first, of said second AND circuit; and one connects by wiring, in the second part of the connectors: the output of request for allocation of priority the corresponding input of account (29 - 30 - 23); the output of the circuit OR the corresponding input for taking into account the request for allocation of level priority (27 - LN2 - 24); the first input of the AND circuit to the corresponding output of the first elementary arbitrator (25 - 31 - 28); and the second entry of the first circuit AND the corresponding output of the second elementary arbitrator (26 32 - 28); and the terminals of the second connector part are connected by wiring, corresponding to the terminals of the first connector part connected to a logic inverter, on the one hand to all the inputs for taking into account priority allocation requests, except that corresponding to the processing unit considered, and on the other hand all the entries for taking into account the request for allocation of level priority except that corresponding to the processing unit considered (23 - 23a and 24 - 23a).