FR2487545A1 - APPARATUS FOR CONVERTING DECIMAL NUMBERS BINARY CODES IN BINARY NUMBERS - Google Patents

Abstract

THE INVENTION RELATES TO AN APPARATUS ALLOWING TO TRANSFORM BINARY CODED DECIMAL NUMBERS INTO BINARY NUMBERS. IT INCLUDES A MEANS 1 APPLYING BINARY CODED DECIMAL NUMBERS TO ADDRESS STORAGE LOCATIONS OF A MEMORIZATION DEVICE 11, 12 WHOSE LOCATIONS HAVE A BIT STORAGE CAPACITY THAT IS LESS THAN THE NUMBER OF BITS ALL NECESSARY FOR EXPRESS DECIMAL ROWS BINARY CODES (U, T, H, TH, TTH) WHICH MAY REQUEST CONVERSION. A MEAN 31 RESPONDS TO THE APPLICATION OF A PREDETERMINED SIGNIFICANT DECIMAL DIGIT BY SEPARATELY PRODUCING BITS OF A HIGHER ORDER THAN THE BIT CAPACITY OF A LOCATION. MEANS 6, 8 ARE SERVED TO ADD BITS WHEN DECIMAL DIGITS FROM DIFFERENT ROWS ARE SUCCESSIVELY APPLIED TO THE RESPECTIVE LOCATIONS OF ADDRESS.

Description

The present invention relates to an apparatus for

  both of transforming values expressed in decimal form, in which each decimal digit is expressed in binary coded notation, into a form in which the value is entirely expressed in binary notation. It is well known, for example in relation to

  data processing equipment, which need to be

  to kill such a conversion. Typically, the data to apply

  such a device is expressed in decimal notation and, for

  handling, for example for its introduction into the

  same, each decimal digit is separately coded in notation

  binary. However, the data processing apparatus is frequently

  designed so that its internal calculation transactions are

  kill on fully expressed values in the binary code.

  Thus, it is necessary that the decimal values expressed by means of separately coded digits be put in a form

purely binary.

  It has previously been proposed to perform this transformation by solving each decimal digit following its

  binary components, then summing the components

  sultants. It will be admitted that the resolution process must take into account the decimal positional significance of each digit, so that, for example, the value 2 appearing at the rank of the units brings a single binary component 2, while the same value 2 appears at the same rank. dozens speak

4 2

  necessarily by binary components 2 and 2. The proposals

  conversion plans using this resolution process

  There are so-called "search" tables which contain the different binary components referred to the different digits according to their particular decimal places. However, with the

  development of manufacturing techniques for memory devices

  The shape of these devices has changed, and it is desirable to use the storage devices which are available on the market in large quantities for economic reasons. In particular, it is desirable to use

  storage elements in which the memory capacity

  offered is expressed in a number of addressable locations

  each containing a predetermined number of memory positions

  bits. The addresses of the locations are expressed in binary notation and the bit capacity of a location is governed by reference to a power of 2. Thus, in practice, it is common for a storage element to have a capacity of 8 bits for example

  and a total of 512 possible addresses. It should therefore be noted that the use

  The use of coded binary digits to address such a memory raises the problem of their compatibility with the addressing system, the result being that considerable redundancy is inevitable. In addition, the capacity of a storage location is such that fewer positions are available to express binary components at any location than would be necessary to express the decimal number theoretically the

  bigger than the memory can handle.

  The object of the invention is to reduce the redundancy indicated above of the storage element, and to further increase the effective bit capacity of the storage locations. An apparatus for converting binary coded decimal numbers to binary numbers includes: means that successively apply binary coded decimal representations in the positional order of significance to address a memory element having a plurality of addressable locations which are each intended to store the bits of a binary representation of its address, the storage capacity

  bits of the slots being smaller than the number of bits required.

  to express all the bit ranks that may appear in the conversion of all applied decimal ranks; a means that responds to the application of a decimal digit of a meaning

  determined by separately producing the signal order bits.

  higher than the bit capacity of the slots; means that reads the bits of an addressed location according to their

  meaning order and a means that adds up the bits appearing

  when the decimal ranks are successively applied.

  The following description, conceived as illus-

  tion of the invention> aims to give a better understanding of its characteristics and advantages; it is based on the appended drawings, among which: FIG. 1 illustrates, in the simplified form of a schematic diagram, an assembly making it possible to transform a

  value in binary coded decimal representation into an equiva-

  valent expressed in binary notation; - Figure 2 shows a variant of the assembly of Figure 1; and - Figure 3 shows another variant of the assembly. As can be seen in FIG. 1, the conversion circuit uses two decoding elements 11 and 21. Each of these elements is a 512-by-8-bit fixed memory element which has a capacity of 512 slots.

  addressable storage that can each store 8 digits.

  The element 11 has a group of eight output lines 12 and the element 21 has an analogous group of eight output lines 22, the lines 12 and 22 carrying the stored binary digits in an addressed location of the respective element. The locations are addressed by signals applied to groups each having nine lines, address lines 13 being associated with the element 11 and address lines 23 to the element 21.

  addresses being specified according to a binary code having nine bits.

  The contents of the location whose address is represented by the bit signals passing through the address lines 13 and 23 are presented to the output lines 12 and 22 in response to a LEC signal using a control line 4 connected to both of them. elements. Among the lines

  address 13 and 23, which are connected in common, the lines

  respectively associated with the largest binary positional order of the two groups are connected to a command line 38. Of the remaining eight lines of each group, the four lines 13, 23 of each group which have the immediately lower positional order are connected respectively to one at each line of a group of output lines 3 coming from a selection network 1,

  while the remaining four lines 13, 23 of

  positional elements 11, 21 are similarly connected

  to a second group of output lines 2 of network 1. The

  network 1 is conveniently a multiplex switching network

  5, each group being associated with a different decimal digit among the decimal digits constituting the binary coded decimal value to be converted into an equivalent binary value. As shown in

  figure 1, the decimal numerical values represent respectively

  units (U), tens (T), hundreds (H), mifliers (Th) and tens of thousands (TTh) and each digit is expressed by signals of lines representing values 2,

21 2 3

  2, 2 and 23, the convention observed in the drawings being that these

  values increase from the point of view of poaition-

  or rank in the base when read from top to bottom.

  The output lines 12, 22 of the elements 11 and 21 are connected to an addition circuit consisting of an adder 6

  and a sum register 8. The lines 12 of the element 11 comprise

  eight binary rows of lesser significance 2 to 27 and the

  lines 22 of Element 21 include the eight most significant ranks

  28 to 25, the two groups of lines 12 and 22 being connected in a single group of inputs applied to the adder 6. Output lines 7 carry sum component signals representing rows 20 to 215 between adder 6 and the sum register 8, and a row group 10 returns the stored sum components to a second group of inputs of the adder 6 so that

  to allow the evaluation of a progressive total in the

  if that. An additional output line 41 starts from the adder 6 to carry signals of the highest significant order, representing the rank 216, which may appear for example as a result of the addition process, and the line 41 is connected via an OR gate 42 of a logic network 31 and then via a line 30 to the sum register 8. The OR gate 42 allows the generation of signals representing the rank 216, when necessary, directly from the outputs 2 Selection Network 1, and for this purpose a

  second output signal applied to the gate 42 is produced at

  The gate 32 has two inputs: a first

  1 is connected to a line 33 coming from a control circuit 36 and a second comes from another AND gate 34. Three inputs 35 are provided at the AND gate 34, and these inputs are respectively associated with the output lines 2 of the network 1 which carry signals representing positional values of 22 21 and 20 The control circuit 36 consists of a network

  logic designed to produce synchronization signals that allow

  both to validate the various operations of the parts of the conversion circuit to be synchronized. Thus, the control circuit 36 normally forms a part of the synchronization control system

  provided in the data processor with which the conversion circuit

  sion is associated. Typically, the control circuit 36 generates control signals via control lines 37 to control the operation of the selection network 1: on a line 38, so as to provide the ninth most significant address signal of Rank 28 at items 11 and 21; on a line 39, so as to

  provide the read-enable signals on lines 4 of the

  11 and 21; on a line 40, in order to validate the formation of the sum by the adder 6 and the writing of the current total in the sum register 8 (ECR signal); and on line 33, to control the production by the AND gate 32 of the rank signal 216

  from the outputs 2 of the selection network 1.

  Before considering in detail the operation of the apparatus, we will briefly examine the mode of addressing of the decoding elements 11 and 21. The addressing systems and the elements are similar, and it is recalled that each element has 512 addressable locations , the addresses being specified according to the binary code and being expressed in nine bits. Of these addresses, the least significant half will be represented using the bit

  the most representative equal to zero, and the most significant half

  tive addresses auracomme most significant bit, one bit equal

  has a. Thus, the remaining eight bits of an address specify real-

  two memory locations, one in each half of the storage element that constitutes each of the memory elements.

  decoding It and 21, and the particular location actually se-

  will depend on the value of the ninth bit that selects

the desired half.

  Moreover, since a single decimal digit, expressed in binary code, requires four bits (respectively of ranks 20, 21, 22 and 23), then eight less significant bits of an address in each of the elements Il and 21 are constituted. bits of a pair of decimal digits, the binary code components of the decimal digit of lower positional significance occupying the least significant positions, 20 to 23, of the address, while those of the most significant decimal digit occupy the positions of immediately more significant bit rank,

4 7

  2 to 2. It is also important to note that while the four binary components of a single decimal digit are able to represent sixteen values, only ten, from 0 to 9, are actually needed. In particular, this will mean that the sequence of addresses of each half of the element having their least significant bits in the range ... 1010,0000 to ... 1111,1111 does not

  will not be necessary to transform a pair of decimal digits.

  We will now briefly examine the function

  conversion circuit. It is carried out in six steps under control of the circuit 36, each step being for example performed in response to an instruction cycle produced by a processor of

data in a conventional manner.

  Before the start of the operation, or suppose that the digits of the binary coded decimal value to be transformed are applied, as groups of binary signals using the lines 5, to the input of the selection network 1, and that the sum register 8

is reset.

  During the first step, a signal of a line 37 coming from the control circuit 36 is applied to the selection network 1 in order to validate the connection, at the output lines 2 and 3 of the network 1, of the signals present on the lines 5 of the two decimal ranks of less significance, namely the units (U) and the tens (T), so that the eight lines of least significance address 13, 23 of the elements 11 and 21 carry respectively representations number of units and tens digit. During this step, a signal is applied on line 38 so that the ninth address line of elements 11 and 21 is maintained

  at a predetermined level representing a binary value of one.

  Thus, if this predetermined level represents the binary zero value, any location addressed by the signals on the lines 13 and 23 will be in the halves of the two elements 11 and 21 having a lower order of significance and will have a remanent address corresponding to the order of binary significance of the numbers of the

  units and tens of the decimal value to convert.

  A signal is also produced on the line 39 by the control circuit 36 and is sent as an LEC signal on the line 4 in order to validate the reading at the addition circuit 6 of the contents of the particular location of each of the elements 11 and 21.

  addressed by the applied signals. It will be understood that these locations

  ments will contain the binary coding value corresponding to the

  the decimal digits applied, the resulting output signal

  both speaking through signals borrowing the lines of exit

8 1

  12 and 22 as components 2 and 2 5. Finally, of course, at this stage, since the decimal values can only be in the range 00-99, the transformed values can only be in the range 2 to 27, so that the output lines 22 of the element 21 are ineffective during this first step. The control circuit 36 then triggers the second step, during which it transmits a control signal via the line 40 to the addition circuit 6 and the sum register 8 in order to allow the addition circuit 6 to form the sum of the values represented on lines 12 and 22 and the value held at that moment in sum register 8 (which is

  equal to zero for this step), and to allow the resulting sum to be

  aunt present on the outputs 7 be transmitted via the lines 9

  and written in the sum register 8.

  Once the value has been written in the re-

  8, lines 10 authorize the presentation of the value

  written to the addition circuit 6 in the waiting position of the operation

following addition ration.

  As soon as the sum has been entered in the sum register 8, the control circuit 36 proceeds to the third step, during which the selection circuit 6 is conditioned, by a signal borrowing the lines 37, to disconnect lines 2 and 3 the decimal numbers of the units and tens and to connect to

  their place the figures of hundreds (H) and thousands (Th).

  For this step, the signal present on line 38 is also modified to maintain the ninth address lines 13 and 23 of elements II and 21 at the appropriate level to represent the opposite binary value so that the locations of elements II and 21 that are addressed are in the previously unused halves, for example the halves of the more

  significant. As in step 1, an LEC signal is

  11 and 21 by a signal on the line 39 from the control circuit 36, and the content of the address addressed in each of the elements is read via the lines 12 and 22

  to be transmitted to the addition circuit 6.

  Thus, the output signals present on the

  lines 12 and 22 represent the additional binary coded components

  The fourth step follows the addition of these components to those already introduced in the sum register 8, the fourth step being similar to the second step previously described. At the end of the fourth step, the cypher register 8 contains the binary equivalent of the value expressed by the numbers of the thousands, hundreds, tens, and units

of the decimal value.

  The fifth step is then performed and, during this step, the fifth decimal digit (TTh) must be applied so as to address elements 11 and 21. It will be assumed that, in the application of this decimal digit, it is necessary to ensure that the addressed locations within elements II and 21 can not include those already associated with the conversion of any of the preceding decimal ranks. Thus, when the application of the decimal digit tens of thousands to the output lines 2 of the network 1 causes the addressing of a location of a group of locations whose ranks of less significance are in the interval. ..0000 to .... 1001, the lines 3 must transmit signals such that this group of locations is in a hitherto unused part of the storage elements constituted by the elements 11 and 21. For this purpose, the control lines 37 transmit signals which disconnect from lines 2 and 3 the decimal digits of the hundreds and thousands and, in their place, connect to the lines 2 the number of tens of thousands, while connecting the lines 3 to a level of appropriate voltage,

  for example to simulate bits of value "ud".

  Mande 38 may also be intended to keep the most significant address bit at the value "one", and in this manner, the addresses that can be selected for the decimal digit tens of thousands are in the range 1 , 1111,0000 to 1,1111,1001, which, as previously noted, is not

  asked for pairs of previous digits.

  As in the case of the first and third steps described above, the control circuit 6 also produces

  the LEC signal on lines 39 and 4 so that the value of.

  conversion in binary terms is produced on the output lines 12

  and 22 elements 11 and 21. However, there is an important

  tinction in this step. Remember that the binary digits available in element 21 can occupy only the positional interval from 28 to 2 5. Thus, rank 216 can not be directly obtained from this element, although it is available at the level of adder 6 if it is produced because of an internal transfer operation inside the adder 6, for example in the case where the decimal digit tens of thousands is 6 and where the decimal value to be converted exceeds In this case, bit 216 is transmitted on line 41, via OR gate 42, and on line 30 to the sum register in the next step. However, as part of the current step, we see that, if the decimal digit tens of thousands has a value of 7 or more, the 216 bit is a direct component of its conversion. On the basis of the single value 7, FIG. 1 shows an arrangement allowing the direct detection of the bit 2. The AND gate 34 of the logic network 31 is intended, by connecting its input lines 35 to the lines 2 having orders

O 1 2

  of positional significance 2, 2 and 22, to produce an output signal if the digit represented on the lines 2 has the decimal value 7. The output signal of the AND gate 34 is transmitted to the AND gate 32, which is conditioned by a signal borrowing the line 33 to indicate the presence of the decimal digit tens of thousands on the address lines 2, from the control circuit 36 to allow the door 32 to let a signal pass during this fifth stage . Thus, if the number of tens of thousands has the value "7", the output signal of the AND gate 32 is transmitted via the OR gate 42 so as to introduce the bit 2.6 in the sum register 8. It will be admitted that the other digits decimals "8" and "9" of the decimal positional order tens of thousands can also be brought to

  generate bit 216 via additional logical gates

loggages at doors 32 and 34.

  The sixth and final step of the conversion is a repetition of the second and fourth steps and aims to allow the sum of the resulting binary components of the fifth step to be added to those produced in the previous steps, so that at the end of the sixth step, the sum register 8 contains the desired converted value, which can then be extracted from the register by conventional read connections which are not

shown in Figure 1.

  It will be noted that, on examining the description

  that the apparatus of the invention has two particularities

  permitted by the conversion of more than two pairs of deci-

  sore by a pair of decoding elements having an address capability

  limited. The first concerns the possibility of selective

  the expressions given in decimal digits to transform them into binary code so as to validate the addressing of locations of the decoding elements that would otherwise be unused. The second particularity concerns the existence of means making it possible to produce the components in binary code beyond the range of elements of

decoding themselves.

  Another arrangement for producing the bit 216 without having to use the logical network 31 is shown in FIG. 2, which shows only those components of FIG. 1 which are necessary for understanding the variant. This variant is based on the fact that bit 20 does not appear in the conversion of any decimal digit of the decimal rank of tens of thousands. Therefore, an AND gate 45 is inserted in the line 12 of the bit 20 from the element 11 to the adder 6. The

  AND gate 45 is controlled by the appearance of a bi-value bit

  1 on the line 12 of the bit 20 and the signal coming on the line 33 from the control circuit 36. It is recalled that this signal is present on the line 33 at the moment when the decimal digit tens of thousands is treated, and the connection of the line 33 to the AND gate 45 comprises an inverter as shown in Figure 2, so that the gate 45 is conditioned to pass signals on the line 12 of the bit 20 for the purpose of processing the numbers previous decimals of the lower order of positional significance. Thus, the gate 45 is closed during the processing of the decimal digit tens of thousands. However, at this moment, a second AND gate 46, one of whose inputs is connected to the

  same bit output line of element 11, is opened by the application

  cation of the same signal at its second input via line 33. The output of gate 46 is connected to a line 12 of bit 216 to

destination of the adder 6.

  Thus, the addresses of elements 11 and 12 which are selected in the manner described above can not be found

  in the range of 1,1111,0000 to 1,1111,1001 and at these locations

  the memorisation position which, in the case of the deci-

  wrong, was used to contain bit 2, is, in the case of

  number of tens of thousands, used to maintain a

16 16

  Since bit 2 can now be obtained directly from element 11, output 216 of the adder is then connected directly via a line 9 to the register.

  sum 8, and the logical network 31 is no longer necessary.

  In the previous examples, the decimal digit tens of thousands is applied to the lines 2 (Figure 1) in the fifth step of the conversion cycle, while the lines 3

  carry a bit of value one. It will be assumed that the value represented

  The value on lines 3 is actually the complement to one of a fictitious decimal digit "O" equivalent to a number of hundreds of thousands, and it will be understood that the interval of. Decimal values that can be transformed can, in fact, be extended to include a number of hundreds of thousands (HTh) at least up to the decimal value five, as follows. The numbers 0 to 5 of the hundreds of thousands, when less than one complementation to the unit, take the binary values 1111 to 1010; thus, they are in the range 1010 to 1111, which corresponds to the portion of the address range ... 1010, O000 to 1111, 1111 previously noted as not necessarily to be used in the conversion of previous ranks pairs of

  decimal digits during the first four stages of the cycle.

  In addition, the bits of the positional values 20 to 23 are not necessary in the conversion of the decimal ranks of the hundreds of

  thousands and tens of thousands. An appropriate terminal value

  required for the conversion of decimal values is 524 287, that is,

  say a value equal to that represented by 219 minus one unit.

  Thus, to ensure the conversion of deci-

  until this terminal point, the decimal digit of the hundreds of thousands is applied to an additional group of lines 5 (omitted in FIG. 1 so as not to overload the latter) which are connected to the selection network 1. conversion cycle, the number of hundreds of thousands is connected to the output lines 3 of more significant order, but these connections have inversion stages so that the

  lines 3 actually carry the complement to the decimal digit. The lines 2 of the network 1 carry the binary components of the tens

  thousands as before. FIG. 3 shows the additional AND gates necessary to allow the use of the output lines 2 to 2 of the element II to form the binary positional values 2 to 2 in the same manner as that described with reference to FIG. relative to values 20 and 2. As in the case presented in Figure 2,

2 487545

  the output line of the element 11 which nominally carries the output bit 20 is connected via the AND gate 45 to which the

  command line 33 of "fifth cycle" is connected through

  intermediate of an inverting input so that the gate 45 is open throughout the preceding cycles so as to pass the output signal 20 to the adder 6. In the same way, the AND gates 47 and 48 also receive the signal from the

  line 33 via inverting inputs and are respectively con-

  connected to the nominal outputs 21 and 22 of the element Il so

  to transmit the bits of these orders of meaning to the addition-

  6. Then, when line 33 carries the signal

  cycle ", the doors 45, 47 and 48 close and doors 46, 49 and 50, which are respectively connected to the nominal outputs 21 and 23 of the element 11 as well as to the line 33, open in order to allow the transmission to the adder 6 of bits

  finding in these positions addressed locations, respectively

16 17 18

  The selection network is conveniently a multiplex switching device for selecting decimal digits in pairs for connection to lines 2 and 3 (FIG. as the conversion cycle progresses. It is noted that the complement to the number of hundreds of thousands is easily obtained by the inclusion of inverters in the bit lines of the numbers at their level.

  connection with the multiplexed switching units. We also note

  whereas the figures of hundreds of thousands of values 6 to 9 inclusive can not be processed in the unused addresses of elements 11 and 21 in the range of 1,1010,0000 to 1,1111, 1111 it there is another group of unused addresses in the range of 0.1010.0000 to 0.11111.1111. It is thus seen that by the inclusion of a logical network (not shown connected to the digit input lines hundreds of thousands of the selection network 1 and made active by the "fifth cycle" signal of the line 33 , the decimal values 6 to 9 can be detected and translated to produce address values, for example, from the range 1010 to 1101. Similarly, the detection of these values can also be used to invert the input address of the most significant order applied to elements 11 and 21 by a simple gating operation, so that all decimal values corresponding to the number of hundreds of thousands produce address components so far unused As noted above, decimal values exceeding 524 287 require the creation of a 2 bit 9. Since bit 23 can not be produced in these cases, the nominal output 23 of the element 11 can be used to produce bit 29 in the same way that bits 216 to 218 are produced. Figure 3 shows, by dashed lines, a pair of doors

  additional resources for this purpose.

  Ai n si, the description that has just been given

  illustrates that the fifth and sixth decimal numbers, of the order

  positional meaning of tens of thousands and cen-

  some thousands, may be converted into a binary converter with a nominal capacity of only four decimal digits by a translation process of decimal digits

  and re-allocation of the order of binary significance of one or more

  positions in a stored word having a bit capacity less than that required for the processing of all the bit ranks necessary for the conversion of the decimal value of the

highest rank.

  Of course, those skilled in the art will be able

  to imagine, from the devices whose description comes

  to be given as merely illustrative and not limiting, various variants and modifications not outside the scope of the invention.

Claims (5)

  An apparatus for converting binary coded decimal numbers to binary numbers comprising means which applies binary coded decimal digits to address storage locations of a data storage device, characterized in that the bit storage capacity locations of the storage device (11, 21) is smaller than the number of bits   necessary to express all positional ranks in deci-   wrong binary code (U, T, H. Th, TTh) that can request the conversion   sion and in that a means (31, 45-50) is   the application of a decimal point of   determined by separately generating these higher order bits than the bit capacity of a slot, the apparatus further comprising means (6, 8) for adding bits read when decimal digits of different ranks are   successively applied to respective locations of address.   Apparatus according to claim 1, further characterized in that the means which separately produces higher order-significance bits includes means (40-50) for re-allocating the binary positional significance of storing bits within a location according to the order   decimal positional meaning of a decimal digit applied.   Apparatus according to claim 1, further characterized in that the means which separately produces bits of a higher order of significance comprises a logical network (31) which   corresponds to a representation in decimal digits of a pre-   determined a predetermined decimal positional position by producing a signal having a binary positional order of significance plus   higher than that shown in the bits read at the addressed location.   Apparatus according to claim 1, characterized in that   in addition to the representation of decimal digits   plicated into pairs of successive positional significance orders   higher, and includes means (36, 38) which is actuated when the decimal ranges comprise an odd number so as to produce a predetermined value to be applied   in order to present a fictitious decimal place of the order of signifi- highest decimal cation.   Apparatus according to claim 1, further characterized in that the allowed location addresses are in binary notation and include means (36) operable upon application of at least one decimal digit applied consecutively a meaning order greater than the least significant order so as to modify the applied binary coded value to address locations that are in an interval   addresses which can not be addressed by means of decisive previously applied ailments.