FR2484672A1 - Calculator module for fourier transformation of sample data - has identical real and imaginary data channels containing arithmetic processors and connected to junction circuit - Google Patents

Abstract

The appts. is used to determine the discrete Fourier transform for a time series of samples. The 'root 4' algorithm is used with a simple and repetitive structure to permit ready testing and fault finding in a radar set. The time sharing system has real and imaginary channels for the respective parts of the samples to be received in series. The channels each contain two calculator blocks which are separated by a common handling block. The blocks contain shift registers in series into which the samples are input and then multiplexed into an arithmetic processor for processing as determined by control signals. The processed signals pass via a memory register into the handling block where they are multiplexed into the second calculator block for application to a multiplication stage.

Description

 The present invention relates to a calculation module for determining the discrete Fourier transform of a temporal sequence of samples in complex form and a Fourier transform computing device using such modules.

 In a number of areas where the spectral analysis of a sampled signal is to be carried out, for example in the radar field, discrete Fourier transform devices of a series of samples are used. Such devices use computational algorithms some of which are now well known. Thus, various so-called "2k root" algorithms have been developed since the development by JW Cooley and JWTukey of the root algorithm 2 or Fast Fourier Transform algorithm (see "An algorithm for the machine calculation of complex"). Fourier would be "Mathematics of Computation, vol 19, 1965, pp. 297-301).

The 2k root algorithms are based on the idea of decoding a discrete Fourier transform of N = 2P terms into 2k Fourier transforms of 2P k terms each. For this, we group together the different terms in 2k packets corresponding respectively to the terms indexes 0, 1, ... 2k-1 modulo 2k
If the root algorithm 2 is still frequently used for the discrete Fourier transform calculation, higher valued root algorithms are increasingly used because they are more efficient and of greater simplicity at least up to a certain point. dimension of Fourier transforms.

 This is the case in particular of the root algorithm 4.

 The subject of the invention is a device for calculating a discrete Fourier transform which, thanks to a particular implementation of the root algorithm 4, has a particularly simple and repetitive, and therefore economical, structure.

 According to the invention, there is provided a calculation module performing additions and subtractions of samples received in series in the normal order and operating in time division, and a discrete Fourier transform calculation device using in a manner repetitive of such modules.

The invention will be better understood and other characteristics will become apparent with the aid of the description below and the accompanying drawings in which - FIG. 1 represents a calculation diagram of the transform of
Discrete Fourier Using Similar Computing Modules - Figure 2 shows the basic diagram of such a module; FIG. 3 is a traffic graph corresponding to the calculation
of a discrete Fourier transform at sixteen points - FIG. 4 is a diagram of a calculation module according to the invention - FIG. 5 is a diagram of clock signals used in the
module of Figure 4; And FIG. 6 represents a device for calculating the transform of
Discrete Fourier according to the invention.

As is known, the different points (or lines) Ak of the discrete Fourier transform of a series of flat-comr samples are given by

 with: k = 0, 1, ..., N-1 and: Wnk = e-2 # jnk / N N being the number of points of the Fourier transform as well as the number of samples in the following.

 The technique for the root algorithm 4 consists in grouping the index terms respectively of the form 4n, 4n + 1, 4n + 2 and 4n + 3.

Thus, the sum Ak is decomposed as follows

 with: k = 0, 1, ..., N-1.

on obtient

By an advantageous grouping of these terms, taking into account that: Wm (k + tN / 4) = [(-1) t] m Wmk for m = 1, 2, 3 and t = 1, 2, 3 and by posing

we obtain

Four Fourier transforms have to be calculated a
N / 4 points. One can obviously repeat the operation until it comes back.

 Four-point Fourier transform decomposition If N is a power of four.

 Thanks to this decomposition, it can be seen that the #logy can be synthesized using simple modules carrying out the four-point discrete Fourier transform algorithm.

 FIG. 1 shows the diagram obtained for N = 16. The modules 10 to 13 and 20 to 23 are all identical and the corresponding flow graph is shown in FIG. 2 for a four-point Fourier transform. The symbols 100 represent multiplications by complex coefficients.

 The graph of Figure 2 is interpreted as follows: each point where a horizontal line and an oblique line meet, going to the right of the drawing, represented an addition, for example at 14 and 16.

Thus, in point 14, we have aO + a2. If we encounter a minus sign on the line conveying data, it is assigned a minus sign, which corresponds to a subtraction, for example at point 15 where we obtain aO - a2. A multiplication by -j is inserted on the last horizontal line. The point A0 of the Fourier transform at four points is therefore given by
A0 = as + a2 + a3.

 That being so, Figure 3 gives the flow graph for a 16-point Fourier transform using this root algorithm 4. This graph is deduced from the # (I) relations after reordering the samples. It can be seen that the calculation of the Fourier transform is carried out using two stages, the first and the third, comprising only four-point Fourier transforms, and one.

step, the second, multiplying by the complex coefficients shown in the figure.

etc.For example, we have B0 = a0 + a8 B'0 = B0
B15 = a7-a15 B'15 = -jB15 C15 = B'11 - B'15

etc.

FIG. 4 represents the diagram of a calculation module making it possible, by sharing with time, to completely perform a calculation step such as the first or the third step of FIG. 3. This module comprises an imaginary channel and a channel. real receiving respectively the imaginary parts zi and real zr samples ancees in series in the normal order of their appearance
a = zrn + jzin.

not
The imaginary and real channels each comprise two calculation blocks, BC1, BC3 and BC2, 3C4 respectively, which are separated by a common switch block BA to the two channels.

The four calculation blocks 3C1 to BC4 comprise similar elements connected in identical manner - two series shift registers (M1, M'1; M2, M'2; ...) - a multiplexer (Mux1 to Mux4) has two related inputs respectively
at the entrance of the first register and the block, and at the exit of the second
register - an arithmetic logical unit (ALU1 è ALU4) carrying out, on
data applied on its two inputs A and B, an arithmetic operation
which depends on the level of the command signal applied to its
SO and S1 command inputs. When the input S1 is not representative
it is constantly maintained at the high level. The operations
performed are as follows S1 = high SO = high -> A plus B
If = high SO = low -> A minus B
S1 = low SO = high B minus A.

Such a unit may for example be constituted by a TTL circuit
SN74S381 from Texas Instruments; a memory register (R1 to R4) connected between the output of the unit
arithmetic logic and the output of the calculation block.

 These four blocks differ, on the one hand, by the control signals applied to their arithmetic logic unit and, on the other hand by; by the number of cells of the shift registers, as we will see.

 The switching block comprises two multiplexers Huai, Mux6 with two inputs whose first inputs are respectively connected to the outputs of the blocks BC1 and BC2 of the imaginary and real channels, whose second inputs are respectively connected to the outputs of the blocks BC2 and BC1 and whose the outputs supply the imaginary parts Cim and real Crm respectively to the inputs of the calculation blocks BC3 and BC4.

 The operation of the assembly will be explained in conjunction with FIG. 5 which represents the clock signals used to control the arithmetic logic units and the switching block.

 It has been assumed, by way of example, that # the calculation module described is the one carrying out the first calculation step of FIG. 3. The sequence of samples> has at the input, a22q samples with q equal here to two sixteen samples. These samples are in x-bit coded form and of course all the links and operations on data in the module of FIG. 4 are carried out on x bits in parallel. The shift registers M1, M'1, M2, M'2 each comprise 22q-1 cells, here eight cells.

 In the first two lines of FIG. 5 are indicated the successive operations performed respectively by the block BC1 and the block BC2. In the calculation block BCI, the clock signal H1 first controls the connection between the input of the first register M1 and the input A of the logic unit ALU1 and, via an inverter, the producing 22qu1 = 8 additions (zi0 + zi8 è zi7 + zip5) between the first eight received samples which appear successively at the output of the register Ml and the last eight received samples which appear successively at the same time on the input of the register Ml . The same additions are carried out simultaneously in the BC2 block under the control of the signals H1, H2 and R3. After having made these eight additions, the calculation block BC1 is controlled by the signal H1 to perform 2Zq 1 - 8 subtractions (ziO - zi8 to zi7 - zi15) between the first eight samples successively at the output of the register M '1 and the last eight samples taken at the output of the register M1.

 Block BC2 proceeds in the same way for the first 2q-2 subtractions under the control of signals Hi to H3.

However, as we can see on the graph of Figure 3, the results of the 22q 2 = last 4 subtractions of the first part of the first step must be multiplied by -j
B'n = -j (Brn + jBin)
jBrn.

We note that this multiplication amounts to inverting the real part and the imaginary part and changing the sign of the real part. For this, during the last 22q-2 subtractions, the signals 112 and 113 take values controlling the subtraction operation B - A for the arithmetic logic unit ALU2, which changes the sign of the real part, and the signal 112 switches the Muxi and Mux6 multiplexers to interchange the real and imaginary parts.

 The calculation blocks BC3 and BC4 perform the additions and subtractions of the second part of the first step of FIG.

These blocks are identical and work in the same way as the BCI block. However, the shift registers M3, M'3 and M4, M-'4 comprise only 22q-2 n 4 cells each. In addition, the clock signal H'1, which controls the multiplexers and arithmetic logic units and which is shown in Figure 5, changes value every four operations. It can be seen that the operating assembly of the module of FIG. 4 is performed synchronously.

 FIG. 6 represents a device for calculating the discrete Fourier transform of a series of sixteen samples using calculation modules of the type represented in FIG. 4.

A first Modal module, which is the one represented in FIG. 4 and which will be of order 22q = 16, realizes the first step of the graph of FIG. 3 and provides the values of the imaginary portions Yp and real Xp of a sequence 22q values, which are sent a complex multiplication stage MC carrying out the second step of calculating the graph of FIG. 3. This stage MC comprises four multipliers 31 to 34, two ROM1 and ROM2 ROMs respectively containing the imaginary parts Ip and real Rp of the multiplication coefficients, two arithmetic logic units ALUS and ALU6, functioning respectively as adder and subtractor, and two output registers R5, R6. This stage carries out the complex multiplication operation:
(p + jYp) (Rp + jlp) = (0pEp - YpIp) + j (XpIp + YpRp).

The complex values obtained are sent to the inputs of a second Modl calculation module of the same type, but of order 22qu4 = 4 (two-cell input shift registers). This calculation module performs the third step of the graph of FIG. 3 and provides the different points of the Fourier transform.

It is clear that, for Fourier transforms at a higher number of points N (N being a power of four), it would suffice to add higher order calculation modules before the module Mod1 of FIG. 6, each module being separated from the next by a complex multiplication stage of the type of the stage MC. It is also possible to use the computing device of FIG. 6 at sixteen points as basic module for an arrangement according to FIG. 1, for sixty-four samples, and so on. In the case where N, every year being a power of two , is not a quarry power, we would arrive at the penultimate stage, an eight-point transform for which we can use, for example, either the root algorithm 2 giving a decomponion in two transforms at four points, the algorithm of
Winograd at eight points.

 One of the advantages of the device according to the invention is, in addition to its simplicity and reduced volume, its great ease of testing and troubleshooting due to its repetitive structure.

 Of course, the described embodiment is in no way limiting of the invention.

Claims (5)

REVENDICATIQNS  1. Order calculation module 22q for the determination of the discrete Fourier transform of a series of samples in complex form by a so-called "root 4" algorithm, characterized in that it comprises in series for each channel , imaginary and real, two calculation blocks (3C1 to BC4) additions and subtractions two by two samples (zin, zrn, Cim, Crm) received in series on their input, said blocks being separated by a block of switching (BA) common to both channels, in that said needle routing block the results provided by the first blocks of each channel, respectively from the imaginary channel to the real path and vice versa, when calculating the 22q-2 last subtractions by said first blocks and in that the first block of the real channel performs a reversal of the terms of said 22q-2 last subtractions.  2. Module according to claim 1, characterized in that each calculation block comprises two identical shift registers (M1, M'1 to M4, M'4) in series, an arithmetic logic unit (ALU1 to ALU4) whose output is connected to the output of the block by a memory register (R1 to R4), an input of which is connected to the junction between the two registers and whose other input is connected to the output of a multiplexer (Muxi to Mux4) with two inputs respectively connected to the input of the block and the output of the second shift register, and in that the arithmetic logic units (ALU1 to ALU4) comprise control inputs (SO, S1) for controlling performing the addition or subtraction, in one order or the other, of the data applied to its two inputs.  3. Module according to claim 2, characterized in that the arithmetic logic unit (ALU1) of the first calculation block of the imaginary channel is controlled to perform successively 22qu1 additions between, respectively, 22qu1 first samples received by the block and the 22qu1 last samples received, then 22q-1 subtractions between, respectively, said first samples and said last samples, in that the arithmetic logic unit (ALU2) of the first calculation block of the real channel is controlled to successively carry out 22qu1 additions between, respectively, the 22q-1 first samples received by the block and the 22th last samples received, then 22qu1 subtractions between, respectively, said first samples and said last samples, the order of the subtraction factors being inverted for the 22q-2 last subtractions, in that the arithmetic logical units (ALU3, ALU4) of the two second The calculation blocks are controlled to perform successively, on each series of 22q-1 values provided by the switching block, 22q-2 additions between, respectively, the 22q-2 first values received and the 22q-2 latest received values. #, then 22q-2 subtractions between, respectively, said first values and said last values, and in that each shift register (M1, M'1, M2, M'2) of the first calculation blocks (BC1, BC2) comprises 22q 1 cells while each shift register (M3, M'3, M4, M'4) of the second calculation blocks (BC3, BC4) comprises 22q-2 cells.  4. Module according to any one of claims 1 to 3, characterized in that said switching unit (BA) comprises a multiplexer (MuxS, Mux6) with two inputs in each of the imaginary and real channels, in that the first inputs of the two multiplexers are respectively connected to the outputs of the first calculation blocks (BCi, BC2) of the imaginary and real channels, and the second inputs of the multiplexers are respectively connected to the outputs of the first calculation blocks (BC2, BC1) of the real and imaginary channels, and in that the switching of the two multiplexers is controlled in synchronism with the calculation of the last 22q-2 subtractions performed by the first two calculation blocks.  5 * Device for calculating the discrete Fourier transform of a series of 22 samples in complex form, characterized in that it comprises in series q calculation modules (mod1, Mod2), according to any one of claims 1 to 4, order 224 22t 1, 22, 22 respectively, each module being separated from the next by a complex multiplexing stage (MC) operating in time multiplex, the real and imaginary parts of the multiplying coefficients being contained in read-only memories (ROMi, ROM2) addressed in synchronism with the appearance of the calculated values at the outputs of the preceding calculation module.