FR2480970A1 - Modular processor for control of gas fired furnace - has memories coupled to real time data acquisition unit - Google Patents

Abstract

The compact and modular processor comprise a coupled to volatile and non volatile memory systems each playing a particular role for data which is input from an acquisition system containing multiplexes and A/D and D/A converters. The data acquisition is organised in real time from modules which provides galvanic isolation and is coupled to the microprocessor via interfaces. The data is transferred by a bus system to which a display and communication unit is coupled to allow communication by an operator via keyboards and displays.

Description

 The present invention relates to a compact industrial processor with permanent saving of parameters.

 More particularly, the invention relates to a compact modular industrial processor, for direct management of an industrial process such as a regulation loop, comprising a low voltage power supply, a microprocessor, a computing unit arithmetic, several memory units, a clock, a timing chain and intermediate adaptation circuits.

 Management systems with microprocessors are used more and more frequently in various fields of industry. However, in most cases, the programming, the production of the interface circuits and in general the implementation of such systems remain complex, long and costly.

 When it comes to making them take into account data from various sensors and many parameters stored in memory to make them perform algebraic calculation chains, the programming of these systems with compact structure is long, even if the those skilled in the art are provided with appropriate development apparatus.

 Furthermore, on a system operating in an industrial environment as a processor, that is to say as a regulator in a loop requiring sorting of information and command outputs, it is sometimes essential to change certain keys of the program and d '' adjust certain parameters to the requirements of the process concerned, then verify by simple tests the proper functioning of the assembly. This is particularly true for systems abandoned to themselves in nature on isolated stations of energy metering, regulation, etc ... or the operational safety must be severely observed.

 The known systems do not allow to efficiently refer to these exeges.

In particular, with the systems of the prior art, it has proved impossible to adapt the parameters in a manner which is both versatile, efficient and safe without leading to excessive complication on the system or a sacrifice in the accuracy of the calculations. Thus, the use of external non-volatile memories for storing parameters liable to be modified, leads in the case of the use of mechanical memories, to an excessive multiplication of the number of counting wheels and, in the case of use of ferrite cores, to an excessive multiplication of bus circuits. Random access random read and write memories, of the RAM type, with low access time, which are usually used for taking data into account variables, remain unsuitable due to their volatility. Even the addition of additional supply batteries does not yet meet the security conditions generally required for backing up data in many industrial process management systems, and in particular does not allow disassembly of the memory block without loss of Finally, non-volatile semiconductor addressable memories, such as Ka type memories, EPROM,
PROM or REPROM generally used for recording program instructions can only be programmed or re-programmed by long operations which cannot be envisaged in situ and which also require external development materials.

 Thus, the systems of the prior art have proved on the whole scit insufficiently compact, either unsuitable for modifying parameters or for testing practices in order to satisfactorily respond to operating conditions in an industrial environment. .

 The present invention aims precisely to remedy the aforementioned drawbacks and to produce a truly compact modular industrial processor which can be constituted in a simple manner from common elements commercially available such as microprocessor, arithmetic calculation unit, time clock real and which allows easy direct management of an industrial process involving both the practice of scientific algebraic calculations with a high level of precision, the voluntary in situ modification of calculation parameters and the saving of said parameters, even in the event of disappearance total of all sources of system power, such as batteries, or - general power.

 These goals are achieved by an industrial processor of the type comprising a low voltage power supply, a microprocessor, an arithmetic calculation unit, several memory units, a clock, a timing chain and intermediate adaptation circuits, characterized in that it comprises at least one non-volatile memory unit with erasable semiconductor and electrically writable by words for storing in a lasting manner, including in the event of the power supply disappearing at the memory circuit, parameters at least some of which are intended to be used by the arithmetic calculation unit in combination with fluctuating digital data emanating from the process to be managed, and electrical erasure and recording means of said non-volatile memory unit controlled directly by the microprocessor.

 Said erasable and word-writable non-volatile semiconductor memory unit can be of the type known by the acronym EAROM or EEROM.

 It should be noted that according to the present invention, memories of this type are not used for recording a program, but are intended for recording or for an in situ modification of calculation parameters with relatively long lifespan. , or information intended, for example, to be collected periodically, or the loss of which affects the operational safety or the economic value of the system. This is for example the case of information corresponding to flow-consumption measurements which must be invoiced to subscribers.

 According to the present invention, the association of such memory units with the microprocessor and the arithmetic calculation unit with which they cooperate is carried out compactly.

 According to a particular characteristic of the invention, the processor comprises a DC-DC voltage converter connected to the low-voltage power source and to the non-volatile memory unit with electrically erasable and writable semiconductor.

 According to another characteristic of the invention, the memory units further comprise at least one volatile random access memory unit, of semiconductor, addressable, read, write and erase, of RAM type, for writing data fluctuating digits emanating from the process to be managed, and at least one non-volatile read-only memory unit, semiconductor, addressable, if necessary programmable or reprogrammable by means of devices external to the processor, of the ROM, PROM, EPROM or REPROM type , for recording programming instructions for process management.

 Thus, all the memory units of the processor according to the invention can be produced in the form of sets of specialized semiconductor memory zones which lend themselves to a compact association within the same set of Storage Management- Calculation.

 More specifically, the Memory-Calculation Management elements comprising the microprocessor, the arithmetic calculation unit, the memory units, the clock, the timing chain, the intermediate circuits for adapting to a system bus and the means erasing and writing of the erasable and writable non-volatile memory unit are arranged and wired in a single module comprising a single printed circuit board.

 The operation is further improved if, on the Management-Memorization-Calculation circuit board, the clock is placed in the immediate vicinity of the microprocessor and the arithmetic calculation unit. This avoids the problems of high frequency radiation.

 According to an advantageous characteristic of the invention, the timing chain comprises means for generating timing signals for the operation of the various members connected to the processor, means for monitoring the chronology and the duration of the operations controlled by the processor and means for triggering a reset of said operations when a fault is detected by said chronology and duration monitoring means.

 The microprocessor which constitutes, within the Management-Storage-Calculation unit, the central element for managing the processor according to the invention, but is assisted both by an arithmetic calculation unit and by memories, some of which constitute memories specific to the storage of parameters, is connected within the processor which constitutes a complete process management system, on the one hand to a coupling block with the process to be managed and on the other hand, to a display block - dialogue authorizing permanent communication or dlszont be naked with rateur.The modular industrial processor compac 5 # 10r # invention can thus be reduced to three basic subsets, although it is also suitable for giving xion to subsets of extension, comprising for example additional memory units.

 More particularly, the processor comprises data acquisition circuits and this organ control, wired on a single printed circuit board grouping together an analog-to-digital converter, programmable interface circuits one-to-one, a circuit of acquisition of real-time and take-off isolation and adaptation modules of industrial process signals to a universal standard seen from the analog-digital converter.

 The data acquisition and organ control circuits may themselves include multiplexing circuits incorporated in the form of unit circuits to each prewired module for adaptation to a signal of the industrial process.

 The processor advantageously comprises a dialogue display peripheral block comprising adaptation interface circuits permanently connected to the system bus supplying all of the management, storage, calculation and input-output elements such as keyboards, printer, displays, transfer memory which can be installed independently of each other on said adaptation interface circuits, or can be coupled by a bidirectional link with a coupling circuit included in the interface circuits of adaptation.

 The invention also applies to a compact modular industrial processor, for direct management of an industrial process such as a monitoring system, comprising a low voltage power supply, a microprocessor, several re memory units, a clock, timing chain and intermediate adaptation circuits, characterized in that it comprises at least one non-volatile memory unit of semiconductor erasable and electrically writable by words to preserve in a durable way, including in case of disappearance of the electrical supply at the memory circuit, digital data serving as a reference for logical operations carried out by the microprocessor, or liable to give rise to periodic readings, and electrical erasing and recording means of- said non-volatile memory unit controlled directly by the microprocessor.

Other characteristics and advantages of the invention will be better understood on reading the description which follows on from particular embodiments of the invention given solely by way of examples with reference to the appended drawings, in which
FIG. 1 is a schematic view of the principle of the various basic sub-assemblies constituting the industrial processor according to the invention,
FIG. 2 is a block diagram, representing the whole of the compact computation management-storage block,
FIG. 3 is a partial view of the diagram in FIG. 2 showing more particularly the non-volatile memories with electrical erasure and recording,
FIGS. 4 and S are diagrams of parts of the acquisition-command block, and
- Figure 6 is a block diagram of the display-dialog subset.

 If we refer to FIG. 1, we see, distributed around the system bus 4, the basic sub-assemblies 1, 2, 3 defining a complete and operational structure of an industrial processor according to the invention.

A main sub-assembly is constituted by a compact block 1 of Management-Storage-Calculation grouping: circuits 14 for adaptation to the system bus 4, a microprocessor 11, an arithmetic calculation unit 12, several memory units 13 and a sub assembly 15 comprising a base clock 151, clock adaptation circuits 152 and timing circuits 153, the memory units 13 are themselves distributed into memory units 131 of EPROM type,
REPROM, PROM or ROMlctest of semiconductor memories of the non-volatile read-only memory type, if necessary programmable or reprogrammable outside the system; in memory units 132 of the RAM type, that is to say of memories & semiconductors of the volatile random access memory type; and in memory units 133 of type
EAROM or EEROM, # ie of semiconductor memories of the non-volatile type but electrically writable and erasable. All the memory units 13 are thus addressable memories with integrated circuit, but of different types and each playing its own function.

 The acquisition-command sub-assembly constitutes an interface block with the industrial process to be managed. The main function of this sub-assembly is the acquisition of live data from sensors and the issuing of orders to operating or permanent information bodies for human use, for example electromechanical meters. This subassembly 3 thus essentially comprises in the incoming direction circuits 31 for multiplexing and analog-to-digital conversion, and in the outgoing direction for circuits 32 for demultiplexing and digital-to-analog conversion, while circuits 33 organize the real time acquisition.

 In addition, the block 3 is equipped with unit modules 34, 35, 36 for galvanic isolation, voltage adaptation and multiplexing, and unit modules 37, 38 for adaptation and galvanic isolation of the outgoing quantities towards the operating parts, not shown.

 Finally, the display-dialogue sub-assembly 2 allows intermittent dialogue between the operator and the system and comprises, on the one hand, an adaptation interface circuit 44 connected to the system bus 4 on a permanent basis and, on the other hand, input / output peripheral elements such as a luminous digital or alphanumeric display 21, numeric keyboard 22, programmed function keyboard 23, printer 24, transfer memory 25, which can be connected independently of one another , temporarily or not, depending on the needs of the operation.

The keyboards 22, 23 and the display 21 allow in particular the entry of the parameters of the process equations, which will be recorded in the memories 133, the possible modification of these parameters, the call of the contents of memories 13 or registers, the verification of the operating sequences, while the printer 24 allows the extraction of partial results or alarms stored during the autonomous operation of the system,
The main sub-assembly 1 of Storage-Calculation Management will be described below in detail with reference to FIGS. 2 and 3.

 The circuits 14 for adapting to the system BUS 4 which notably comprises an address bus 241 and a data bus 242 essentially include an interface circuit 141 interposed between the address bus 41 of the subassembly 1 and the bus d 'system address 24; and an interface circuit 142 interposed between the data bus 42 of the subassembly 1 and the system data bus 242. The interface circuits 141 and 142 allow the amplification and regeneration of the address bus 41 and of the data bus 42 before their distribution on the system bus 4.

 The microprocessor 11 comprises 8 bits in the example considered and is connected on the one hand to the address bus 41 (wires AO-A15), on the other hand, to the data bus 42 (wires DO-D7). The microprocessor It can be constituted, for example, by the 6800 microprocessor from the Motorola Company, or of course a pin-for-pin equivalent.

 Clock circuits 151, 152 allow the delivery of two signals 0 1 and IZI 2, of two-phase type, necessary for the operation of the microprocessor 11.

 A logic circuit 143 for controlling the "address" interface circuit 141 enables the bus 241 to be placed in a high impedance state on reception of a BA signal produced by an inverter 111 from the BA signal coming from of the microprocessor 11.

When the BA signal is transmitted, the bus 241 can then be addressed in DMA mode of direct access to the memory, which makes it possible either to transmit to the outside by the bus 242 of the data coming from the memories 132, 133 or to transmit data introduced by the bus 242 to the latter. The logic control circuit 144 which delivers signals DT (Data Transmitted) and DR (Data Received) allows the switching of the direction of data transmission at the interface circuit 142 The control logic circuit 144 is itself controlled from four signals emitted by either the microprocessor 11 (R / W, R / W and
BA) or by an address decoding circuit 145 (EDS signal).

 The R / W read-write signal and its complementary R / W, obtained at the output of the reading-writing decoding circuit 146 connected to the microprocessor 11, make it possible, as their name suggests, to detect whether the exchanges are in read or write mode.

The signal BA obtained at the output of the inverter 111 and applied to the circuit 144 makes it possible to set the data bus at high impedance. Finally, the EDS signal for selection of external data, supplied by the circuit 145, authorizes the opening of the doors only if an address not found on the module 1 is requested.

 The address decoding circuit 145 makes it possible to make a selection from among the various addressable integrated circuits 131, 132, 133, 134, 12, 153. Furthermore, two additional inputs of the circuit 145 can modify the operation of the latter, Thus, when the modular sub-assembly 1 is used alone, without an external debugging aid module, VMA information indicating whether an address is valid comes directly from the microprocessor 11 which lendgender, and is applied to the circuit 145 On the other hand, the presence of an external focusing aid card sends a VUA signal for validation of the user's address, which VUA signal is taken into account by the address decoding circuit 145 in place of the VMA signal, the contact 148 then being placed so as to connect the circuit 145 to the line VUA. When using an external focusing aid card, the signal CMP makes it possible to double the addressing capacity of the memory units 131. Furthermore, in FIG. 2, the inverter 112 and the amplifier 147 , are simply intended to adapt the BA and VMA signals on the control part of the system bus 4.

 The read-only memory units 131 connected to the address 41 and data 42 buses consist in the example considered by two blocks 1311 and 1312 each formed by an EPROM memory of 2 kilobytes.

These memories 1311 and 1312 are selected respectively by the links CSPROM1 and CSPROM2 connected to the address decoding circuit 145. The layout and the operating mode of these memories intended for recording a program are conventional.

 The random access memory unit 132 also connected to the address 41 and data 42 buses consists of eight 1-kilobit RAM memories addressed simultaneously by the RAMENA link connected to the address decoding circuit 145. However, a terminal 1320 makes it possible to replace an ester memory expansion card of the same type in place of the unit 132. The implantation and the operating mode of the unit 132 in combination with the microprocessor 11 are also conventional.

In addition to the EPROM memory units 131 and
RAM 132, the memory block 13 of the sub-assembly 1 of Management-Storage-Calculation further comprises units 133 constituted by non-volatile memories of the programmable, erasable and electrically reprogrammable type, known under the name EAROM or EEROM. Such memories usually provided for recording program instructions, taking into account their non-volatility, require for their programming specialized apparatus which makes this operation long and expensive. However, in the context of the processor according to the invention, the memories 133 are used not for recording a program, but for storing calculation parameters or data intended to be restored. of the envisaged application, the programming of the memories 133 can be managed directly by the microprocessor 11, which leads to a particularly high capacity of the system. The memories 133 are controlled from the microprocessor 11 in situ by means of a control circuit 134 which essentially comprises a programmable interface adapter circuit (PIAI) addressed by the wire CSPIA1 from the address decoding circuit 145 The electrical erasing voltage of -30V is itself obtained by a continuous converter 135 from the supply voltage of the integrated circuits of the system (5V). The voltage converter 135 can advantageously be placed on the card. single printed grouping all the elements of the sub-assembly 1, because this makes it possible to reduce the bulk at the level of the connector and to reduce the problems of sharing the supply wire leads.

In FIG. 3, the memories 133 used in the context of the example considered are of the 1024 x 4 bit type. As a result, two memories 1331 and 1332 of this type used in combination make it possible to achieve compatibility with the chosen 8-bit microprocessor 11. The address bus 41 can be directly connected to memories 1331, 1332 (wires AO to A9). The data bus 42 is itself connected in such a way that the 4 most significant bits are distributed # on the memory 1331 while the other four bits are distributed on the memory 1332. The R / W signal for read / write is itself - even directly applied from the microprocessor li on the WE input of memories 1331 and 1332. The writing, erasing and reading of memories 1331 and 1332 are controlled by two control signals C1 and C2 generated by the circuit 134 programmed so that its PAO and PA1 wires (Fig. 3) transmitting signals C1 and C2 are outputs. The truth table of signals C1 and C2, is summarized below
Ci C2
Top Top Clear by
Low High Erase by memory
High Low Writing
Down Down Reading
The circuit 134 for controlling the memories 133 is addressed by the CSPIA wire, connected to the address decoding circuit 145. The selection of the memories 1331 t 1332 from the CS EEROM link connected to the address decoding circuit 145 is itself synchronized by passing through a D 136 flip-flop controlled by clock 151 to produce two signals CS EEROMlet CS EEROM2 applied respectively to memories 1331 and 1332.

 The processor according to the invention allows, in addition to the presence of the memories 133 for storing parameters, a use made easier, yes 1 user due to the presence in the main subassembly of the arithmetic calculation unit 12, which can be, for example, constituted by the circuit AMD 9511 of the Company AMD, or naturally a spindle equivalent for spindle. Such an arithmetic calculation unit -12 allows, in association with the microprocessor 11, of sulvre, real-time fluctuations of a physical phenomenon & control, including a strongly no. linear which requires both complex and precise computations. The arithmetic calculation unit 12 incorporated in the system thus allows floating point calculations and greatly reduces the programming work of the user.

The arithmetic calculation unit 12 connected to both the address bus 41 and the data bus 42 is controlled by the circuit 121 for controlling the arithmetic circuit. The APUENA line coming from the address coding circuit 145 and the R / W read / write line allow the selection of the arithmetic calculation circuit 12 via the control circuit 121 essentially comprising three doors.
NO AND.

 The control circuit 121 performs a decoding allowing the emission of three composite signals, namely a signal CSAPU for selecting the calculation circuit, a signal WRAPU for writing in the calculation circuit, and a signal RDAPU for reading in the circuit Calculation. The circuits 152 associated with the base clock 151 ensure the production of a signal ~ 3 asynchronous with respect to the three preceding signals and the frequency of which is twice that of the signal ~ 2 produced by the base clock 151. The signal clock 0 3 cadence the internal sequence of operations of the arithmetic circuit 12.

 The clock and timing circuits 151 to 154 are all also arranged on the same printed circuit board carrying the elements already described with reference to FIGS. 2 and 3. However, these clock and timing circuits are preferably arranged at immediate proximity of the microprocessor 11 and the arithmetic calculation circuit 12 in order to reduce as much as possible the sensitivity to parasitic signals, and to HF radiation.

 Furthermore, since the reference and synchronization clocks with the data bus 42 included in the circuits 151, 152 (fig. 2) are identical, any modification of their frequency is prohibited. For example, for direct access to memory (DMA), generally in the case of access to a memory expansion unit, line BA allows the microprocessor to be stopped without any intervention on the condition of clocks.

 The timing of the system program is achieved by means of a time calculation circuit 153, program by the microprocessor 11. This circuit 153 is selected by the line "Timerena" from the address decoding circuit 145. The time calculation circuit 153 also performs the "watchdog" function which ensures the security of the system by periodically giving, for example every second, through the security reset circuit 154, the RESET line to the low level, except reprogramming by the microprocessor 11. Thus, any random #buckling in the software or any random shutdown of the microprocessor will cause a complete reset of the system state. In addition, the non-volatile memories 133 can themselves serve as a reset counter. These memories 133 of the EEROM or EAROM type can thus be used both as a medium for storing the data entered constituting calculation parameters, or serving as a reference for logical operations carried out by the microprocessor, and as a support for the storage of information such as, for example, the number of resets carried out in order to serve as control strips which can give rise to periodic readings. The memories 133 finally lend themselves to the implementation of system operation tests.

 In the example described, the grouping on the same circuit board not only prints microprocessor and EPROM memories 131 and RAM 132, but also calculation circuit # arithmetic 12, EAROM memories 133 and all the timing circuits or control unit belonging to Subsystem 1 of Nemorisation-Calculation Management of fig. 2 allows a reduction in both wiring, interference sensitivity, connection problems and adaptation circuits to the system bus, which contributes both to a reduction in the cost and an increase in the reliability of the system.

 As already indicated, the implementation of an arithmetic calculation circuit 12 makes it possible both to increase the processing rate of the processor, and to decrease the arithmetic operation software. An example of use is described below.

The arithmetic processor 12 (APU) behaves, seen from the microprocessor 11, like a RAM memory
(read-write) of two 8-bit words. The first will be called a control word when it is written to the arithmetic processor 12, and a status word when it is read from said processor 12. The second will be called the data word in both cases. The calculations are done on 32 bits. It is therefore necessary to enter four data words in succession in the arithmetic processor for a variable. This is done by an input subroutine.

You can enter up to four variables in the arithmetic processor in a LIFO type stack (Last data entered, first output). The variables can be output to the microprocessor 11 by successive reading of four 8-bit words & the address corresponding to the data word by an output subroutine. The operation, by the so-called "Reverse Polish" method, is then performed between the two variables
TOS (Top of stack) and NOS (Next in stack). The result is in the TOS.

 The operation is launched by sending the code corresponding to the command address after verification by reading the status word of the availability of the APU.

 It turns out that all of the operation and management subroutines of the calculation block 12 can occupy a memory space of the order of 250 bytes, all the arithmetic and mathematical functions being programmed definitively and being available for the program. of use.

For example, a program linearizing a sound
of platinum temperature 10OSL from its resistance according to the
formula: g = g1 + 02 R + 93. R2 (1)
approximately occupies 40 bytes of memory.

In addition, the management of EEROM memories
133 can also be performed by a subroutine
simple. The sequence of changing parameters in
memories 133 can include the following operations
your
10) Initialization of the peripheral circuit
memory control 133.

20) Writing of four bytes in the memory
re 133 to know for each byte
a) Clearing the byte
b) waiting for 600 ms
c) fictitious reading
d) writing of the byte
e) waiting 65 ms
f) fi # ctive reading
The description of the acquired subset
tion order will now be made with reference
in Figures 4 and 5.

Blocks 31 & 33 of Figure 1 symbolizing
the main functions of the acquired subset
tion command 3 are arranged on the same card 30 of
plug-in printed circuit to which the various adapter and isolation modules are also connected
34 34 pre-wired. All connections between
modules 34 to 38 and the other elements of the card 30
are carried out via a bus 39 compor
as many as 16 wires in the example described: a return wire
ground, 39c analog channel return wire, four-wire
selection of modules 34 38, eight bi-data wires
directional logic and two interrupt wires.

 The system address bus 241 and the system data bus 242 arrive respectively on interface circuits 313, 314 which amplify and reflect the signals and to which are connected a local address bus 341 and a local data bus 342.

The local address bus 341 is distributed in part by the address wires AO, Ai, on an analog digital converter 311 and a universal programmable interface circuit 312 and on address decoding circuits 315 providing signals
CNAENA and PIAENA allowing the selection of the converter 311 or of the interface circuit 312. The local data bus 342 is itself distributed on the converter 311 and the interface circuit 312.

The digital-analog converter 311, which, in the example considered is of the 12-bit type compatible with an 8-bit microprocessor, receives the signals from the analog bus line, three control signals, namely the read-write signals.
R / W, address AO and clock 0 2, and a link
STS with the programmable interface circuit 312 allows the latter to monitor the state of the converter 311.

 The universal programmable interface circuit 312 has four lines which send an address to the adaptation modules, eight lines which can be programmed as input or output to collect or send logic information and four lines which make it possible to manage the circuit 33 giving real time and including its own frequency reference such as quartz 331.

 The adaptation and isolation modules 34 to 38 are specialized so as to allow either the acquisition of an analog quantity (module 35) or the acquisition of a digital quantity characterized by its state or its frequency (module 36 ), either the control of all-or-nothing components (module 37), or the control of analog quantities (module 38).

 Each module 34 to 38 includes a part 324, 324 'for decoding the address of the address bus 39a (FIG. 5).

The decoding circuit 324 'provided for adaptation to an analog input makes it possible to control a switching device 323' making it possible to switch an analog quantity on the analog bus wire. This corresponds to the case of a module of the type of module 35. The decoding circuit 324 provided for adaptation to a digital input makes it possible to open flip-flops three states 323 which send digital information to the data bus of bus 39. This corresponds to the case of a module of the type of the module 36. A decoding circuit likewise makes it possible to memorize in registers the digital data present on the data bus 39b of the bus 39 in the case of a module of the type 7 for an all or nothing order.

 The galvanic isolation device of a digital processing module such as 36 inserted between the adaptation unit of the module 321 and the switching device 323 comprises optoelectric couplers 322. In the case of an analog processing module such that the galvanic isolation is then ensured by an isolation amplifier 322 ′.

 The area 321, 321 ′ of a module 34 to 38 intended to carry out the adaptation to the physical process can for example carry out the transformation of an incoming analog signal, transmitted into proportional current, into a voltage between 0 and 5 volts ( circuit 321 'of module 35) or the transformation of an incoming frequency into an 8-bit digital word, or the transformation of an outgoing digital word into an analog organ control voltage (module 37).

 The display-dialogue sub-assembly 2 which can have various embodiments, is shown in FIG. 6 in an embodiment comprising a single integrated circuit card bringing together the control circuits of various peripherals. Depending on the applications envisaged, the peripherals can either be permanently installed, or connected on demand, or even remotely connected by a bidirectional link. An integrated display 21, possibly supplemented by a keyboard 22 and a printer 24, must be provided in the case of a processor carrying out data acquisition with processing. In the case of counting for example, a transfer memory 25 or a printer 24 must make it possible to periodically empty the content of memory areas of block 13. In the case of a simple regulation process, a keyboard and a display are by no means permanently essential. In applications which require only occasional dialogue, a terminal can be connected on demand, for example by a bidirectional link 231 connected to the interface circuit 30. Such a terminal may include in particular a printer, a display, a double numeric keypad and functional program, permanent storage memories, a magnetic cassette, and revolves around a microprocessor whose software can be oriented towards a specific application comprising, for example, statements of processed information.

There is shown in FIG. 6 of the address interface and data interface circuits 441 and 442 connected on the system bus making it possible to regenerate and format the signals of the system address bus 241 and of the system data bus 242. The control signals and the system clocks are regenerated in the
system control interface circuit 443. A cir
cooked address decoding 444, to which are applied
the control and local address bus signals 541 coming from the interfaces 443, and 441, delivers two signals CCA1ENA
and CCA2ENA which select one of the two management blocks
The keyboard display 210 and 220. The first keyboard display 210 circuit manages a set of af
7-segment fileers and performs multiplexing in
time to reduce the consumption of displays
21.Circuit 210, programmable by microprocessor
11 and connected to the local data bus 542 from the
circuit 442, cooperates with power interface circuits 211 and 212 for controlling the segments
display. The decoded data being sent on the 7
segments of all displays by circuit 211,
only a common anode will be excited by circuit 212,
the scanning of the different anodes being periodic.

The second circuit 220 manages two keyboards which can each include sixteen keys. Sixteen light emitting diodes
centes controlled by a multiplexing circuit, such as
the displays 21 are associated with one of the keyboards and supplied from an amplification circuit 222.

 The taking into account of a pressure on a key of one of the two keyboards is done by a matrix scan. A high level is sent to the entire column of keys. If there is a key press said high level will be seen on a line. The scanning of all two keyboards is done in 100 ms with recognition of twists. Any key press interrupts the normal course of the calculation or program and the needle to the adapted treatment subroutine, via the interrupt line.

 An example of application of the industrial processor - previously described will now be presented below.

 According to this example, the processor is used as a gas flow regulator-counter in cooperation with a nozzle of variable geometry, such as that described in French patent application No. 76 04 039. It is known, in fact, that a nozzle of which the geometry can vary not only allows the regulation of an expansion but also the counting of the gas which passes, insofar as the geometry of the nozzle and the physical conditions of the gas upstream thereof are known.

The formula for developing the volume flow is as follows

oê Pe = upstream pressure
Te = upstream temperature
Sc = nozzle neck section
K1 and Kn are coefficients depending on the upstream pressure, the density of the gas, and the temperature.

More specifically Sc = LD tg α (1 - L tg α) (3)
2 D 2 where L = axial travel of the nozzle sealing cone.

D = base diameter of the nozzle neck, without warhead,
angle = angle of opening of the warhead
K1 = A + BPe + CPe2 with Pe 3 upstream pressure
A = Ai + A2 tn + A3 fn2 + A4fn3 en = 1,293 xd
d = density of
A1, A2, A3, A4 are gas coefficients
empirical
B = f (T) of the 2nd degree
C = f (T) of the 2nd degree
Kn = 1.80505 x 107
The processor takes into account three quantities
physical represented by
temperature represented by the resistance of a platinum probe
- pressure represented by the 4 & 20 mA current of a sensor
- displacement represented by the current - lo mA to + 10 mA
from another sensor.

 These signals enter the acquisition-command module 3 where they are adapted to the standard lv to 5V of the analog-digital converter 311, in the circuit 321 ′ of the adaptation module 35 then isolated in the circuit 322 ′, finally converted into a numerical value in the converter 311. We see here the advantage of the adaptation modules of the acquisition-control card.

 From this physical data, the processor calculates the bit rate. The calculation requires not only the knowledge of an arithmetic library but also that of the calculation of a square root and a tangent. To perform these heavy calculations, the arithmetic processor only requests a series of instructions sending it an adequate code. The arithmetic processor automatically readjusts the location of the decimal point, without external software, so that the calculations are made with maximum precision.

 The value of memories 133 of the EAROM type is highlighted by the large number of modifiable coefficients: scales of the sensors for precise calibration (6 pieces of information), coefficient Kn of calibration of the nozzle, density of the gas. These values must be given with a minimum precision of 4 digits, which, according to the prior art, would amount to taking into account 8 x 4 = 32 coding wheels whose volume, wiring and handling are important, to have a -device saved in all circumstances, in the event that the memories 133 are not present.

 Certain more complex configurations require the saving of a larger number of parameters which is made easy with the presence of the EAROM memories.

 This application to the regulator-meter can have a local display allowing to know the Instantaneous flow, the daily accumulation, the minimum and maximum flows, etc. The choice of display is made by the luminous functional keyboard 23.

If the user only needs to know one value, for example the flow rate, the local keyboard can be deleted and a plug-in keyboard will be made available to the operator during the calibration of the nozzle.

 In addition, the accumulation can be carried out on an electromechanical counter controlled directly by the sub-assemblies 1 and 3.

 The processor according to the invention can be applied in the same way to other types of systems, such as, for example, a system for driving a glass furnace, supplied with gas, which must be controlled according to the physical characteristics of the gas. The various coefficients entering into the calculation formulas are stored in the memories 133 of the processor. When setting up the regulation, the manufacturer can thus, using the display-dialogue sub-assembly 2 possibly consisting of disconnectable elements, monitor and modify the response of the process as desired in situ. After the debugging, the parameters stored in the memories 133 cannot be accidentally destroyed and the system can operate completely automatically.

 Of course various modifications and additions can be made by those skilled in the art to the devices which have just been described only by way of nonlimiting examples, without departing from the protective framework of the invention.

Claims (11)

 1.; Compact modular industrial processor, for direct management of an industrial process and a control loop, comprising a low-voltage power supply block, a microprocessor, an arithmetic calculation unit, several memory units, a clock, timing chain and intermediate adaptation circuits, characterized in that it comprises at least one non-volatile semiconductor memory unit which can be erased and electrically writable by words for long-term storage, including in the event of disappearance of the power supply at the memory circuit, parameters at least some of which are intended to be used by the arithmetic calculation unit in combination with fluctuating digital data emanating from the process to be managed, and erasing means and electrically registering said non-volatile memory unit directly controlled by the microprocessor.  2. Industrial processor according to claim 1, characterized in that the erasable semiconductor non-volatile memory unit electrically writable by words is of the EAROM or EEROM type.  3. Industrial processor according to claim 1 or claim 2, characterized in that it comprises a DC-DC voltage converter connected to the low-voltage power source and to the non-volatile semiconductor memory unit. cff-- cable and electrically writable.  4. Industrial processor according to any one of claims 1 & 3, characterized in that the memory units further comprise at least one volatile, semiconductor, addressable random access memory unit, for reading, writing and erasure, of the type RAM, for recording fluent digital data emanating from the process & managing or directing sty, and at least a non-volatile, semiconductor readable memory unit, addressable, if necessary programmable or reprogrammable by means of external devices to the processor, of the ROM, PROM, EPROM or REPROM type, for writing programming instructions for managing the process.  5.- Industrial processor according to any one of claims & 4, characterized in that the management, storage and calculation elements comprising the microprocessor, the arithmetic calculation unit, the memory units, the clock, the chain of timing, the intermediate adaptation circuits & a system bus and the electrical erasing and recording means of the erasable and writable non-volatile memory unit are arranged and wired in a single module comprising a single printed circuit board.  6. Industrial processor according to claim 5, characterized in that on the circuit board Printed with Gsstiona flemorisation - Calculation, the clock is placed in the immediate vicinity of the microprocessor and the arithmetic calculation unit.  7. Industrial processor according to any one of claims 1 to 6, characterized in that the timing chain comprises means for generating timing signals for the operation of the various organs connected to the processor, means for monitoring the chronology and the duration of the operations controlled by the processor and means for triggering a reinitialization of said operations when a fault is detected by said chronology and duration monitoring means.  8. An industrial processor according to any one of claims 1 to 7, characterized in that it comprises data acquisition and organ control circuits, wired to a single printed circuit board grouping together an analog-to-digital converter, universal programmable interface circuits, a real-time acquisition circuit and pre-wired modules for isolating and adapting signals from the industrial process & a universal standard seen from the analog-digital converter.  9.- Industrial processor according to any one of claims 1 to 8, characterized in that it comprises circuits for data acquisition and control of organs comprising multiplexing circuits incorporated s in the form of unit circuits & each pre-wired adaptation module & a signal of the industrial process,  10.- Industrial processor according to any one of claims 5 to 9, characterized in that it comprises a peripheral display dialogue unit comprising adaptation interface circuits permanently connected to the system bus supplying all of the elements Management - Storage - Calculation and input-output elements such as keyboard, printer, display, transfer memory which can be implemented independently of each other on said adaptation interface circuits, or can be coupled by a bidirectional link with a coupling circuit included in the adaptation interface circuits  11.- Compact modular industrial processor, for direct management of an industrial process such as a monitoring system, comprising a low-voltage power supply, a microprocessor, several memory units, a clock, a timing chain and Intermediate adaptation circuits, characterized in that it comprises at least one non-volatile semiconductor memory unit that can be erased and electrically writable by words to conserve sustainably, including in the event of the disappearance of the electrical power supply level of the memory circuit, digital data serving as a reference for logical operations carried out by the microprocessor, or liable to give rise to periodic readings, and means for erasing and recording electrically of said non-volatile memory unit directly controlled by the microprocessor.