FR2479508A1 - GROUP-ELEMENTS DATA PROCESSING DEVICE AND SWITCHING CIRCUITS REDUCING THE NUMBER OF CONNECTIONS BETWEEN ELEMENTS - Google Patents

Abstract

THE INVENTION RELATES TO A MATRICAL PROCESSOR IN WHICH EACH SUB-MATRIX OF PROCESSING ELEMENTS IS ASSOCIATED WITH A GROUP OF PROCESSING ELEMENTS OF CONTROL BITS. CONTROL CODE PROCESSING ELEMENTS P HAVE 18 NORTH-SOUTH CONNECTIONS BUT HAVE NO EAST-WEST CONNECTIONS. INSTEAD OF THIS, THE NORTH-MOST ELEMENT IN EACH GROUP IS CONNECTED DIAGONALLY 20 TO THE SOUTH-MOST ELEMENT IN THE NEIGHBORING GROUP, SO AS TO ALLOW THE SERIAL TRANSFER OF CONTROL CODES VIA THE NORTH- CONNECTIONS. SOUTH 18 AND DIAGONAL CONNECTIONS 20 BETWEEN ADJACENT GROUPS IN EAST-WEST DIRECTION.

Description

The present invention relates to treatment devices

  data of the type comprising a plurality of processing elements

  logically arranged in rows and columns so that each

  have four closest neighbors. Such a device is described for example in British Pat. Nos. 1,445,714, 1,536,933, 2,020,457,

2,019,620 and 2,037,042.

  In such a device, it is usually desired to allow each element to send information to and receive one of its four closest neighbors. In the patents cited above, this result is achieved by connecting each element to its four nearest neighbors via a separate connection line. An object of the invention is to reduce the number of connection lines necessary to ensure the transfer of information between neighboring elements. According to the invention, there is provided a data processing device comprising a plurality of processing elements

  logically arranged in rows and columns, the device is

  tinguishing in that each column is divided into several groups of elements, the elements of each group being connected together so as to allow a transfer of information to the north and south between adjacent elements within a single group of elements. group,

  and the device is distinguished in that it comprises several cir-

  switching buns each having two states, o (a) in the first state, the switching circuits connect the northernmost element in each group to the southernmost element in the adjacent group in the northerly direction , so as to allow information transfer north and south between adjacent groups of the same column, and (b) in the second state, the switching elements connect the northernmost element in each group to the southernmost element in the adjacent group in a westerly direction so as to allow the transfer of information to the east and west

  between adjacent groups of different columns.

  It can thus be seen that the invention replaces several con-

  east-west nexions between elements of an adjacent pair of groups by a single "diagonal" connection between the northernmost element of a group and the southernmost element of the group lying to the west of the group -this. Information is moved east or west by placing the switching circuits in their second state, then making a series of displacements north or south following the diagonal connections. We see that the invention

  significantly reduces the number of connection lines.

  In a particular embodiment of the invention described below, the device comprises a plurality of data processing elements and a plurality of control code processing elements, each control code processing element holding a control code

  (eg parity bits) relative to a specific plurality of

  of data processing elements. In the embodiment described, the invention is used to reduce the number of connections between the control code processing elements. However,

  data processing elements are connected in the classical way

  that is, each element has a connection line

  distinct with each of his four neighbors.

  It should be noted that the phrase "logically arranged" is intended to indicate that the arrangement of elements in rows and columns does not necessarily constitute a real physical provision. In practice, the elements may be mounted on printed circuit boards in any convenient hardware configuration, with appropriate electrical connections forming the desired logical arrangement. Similarly, it will be noted that the terms "north", "east",

  "south" and "west" are used in this description to simply describe

  the logical relationship between the elements and should not be taken to imply any particular material provision.

  The following description, designed as an illustration

  of the invention, aims to give a better understanding of its features and advantages; it is based on the attached drawings, among which

  Figure 1 is an overall block diagram of the

  operative part; Figure 2 shows the connections between the data processing elements, the parity processing elements and the parity checking circuits; Figure 3 shows the connections between the data processing elements; Figure 4 shows the circuit of one of the elements of

  data processing which allows the selection of data inputs

  Figure 5 shows the connections between the parity processing elements; Figures 6 and 7 show two possible states of a switching circuit; Fig. 8 shows the circuit of one of the parity processing elements for selecting parity bit entries from neighboring elements; and Figures 9 and 10 illustrate two possible ways of

  connect parity processing elements consisting of

  large scale integrated circuit chips.

  FIG. 1 shows a data processing device comprising 4096 identical data processing elements D arranged along 64 rows and 64 columns. Each element may have the form indicated in the patents cited above and will not be described in detail. However, in summary, each element

  contains a data memory with a large number of

  one-to-one addressable bit mappings, various one-bit internal registers, a single-bit binary adder, and various gates for controlling the movement of data between the memory, the register, and the adder. D elements are controlled by signals that are broadcast in parallel to all elements, so

  that all the elements perform the same fundamental operations-

  but on different data.

  We see that the set of elements D is subdivided into sixty-four square subsets 10, each of which contains 8 x 8 elements. Each subset is associated with a group 12 of

  eight parity processing elements P, one per row.

  As described in the cited patent 2,037,042, the parity processing elements P are substantially identical to the data processing elements D, and are controlled by the same control signals, so that each processing element of parity performs basically on the parity bits the same manipulations as

  the data processing elements perform on the data.

  For example, if a data bit is transferred from the memory of each data processing element to one of its internal registers, the corresponding parity bit is transferred from the memory

  each parity processing element in the internal register corresponds to

of this element.

  Figure 2 shows one of the rows of data processing elements of a subset, and the corresponding parity processing element. Output data bits from the eight data processing elements are supplied to a parity check circuit 14, where they are monitored for the bit of

  corresponding parity from the parity processing element.

  If there is an error, the control circuit 14 produces an error signal. The parity check is well known, so it is not

  it is not necessary to describe circuit 14 in detail.

  Figure 3 shows how the data processing elements are connected together to allow data transfers between them. Each D element is connected to its four closest neighbors to the north, east, south and east.

  west. An exception to this provision is found on

  of the whole, o, of course, the elements have less than four neighbors. However, the elements on the north edge of the assembly can be connected to those on the south edge, so that each column actually consists of a loop

  elements. Similarly, the rows can be connected in loops.

  The direction of the transfer of data between

  This is controlled by a routing code that is broadcast to all elements in parallel. The routing code is made up of two bits, the meaning of which is as follows Routing Code Direction 00 North 01 East South West As shown in Figure 4, each data processing element contains a multiplexer 16 having four inputs 0, 1, 2 and 3 which are connected to receive data from the four neighboring elements south, west, north and east, respectively. The multiplexer 16 is controlled by the routing code, so that it chooses one of the four inputs according to the binary value of this code. For example, if routing code is 00, input 0 is selected, so each element accepts data from its

  south neighbor. It follows that the datum circulates towards the north.

  Figure 5 shows how the parity processing elements P are interconnected. Inside each

  group 12, they are interconnected by north-south connections.

  However, there are no east-west connections. As a result, the transfer of parity bits between adjacent groups of parity processing elements in the east-west direction is obtained by diagonal lines that connect the northernmost element.

  in each group with the southernmost element in the group adja-

  cent located to the west. Switching elements 22 are provided to determine whether the parity bits are to be moved between adjacent groups in the north-south direction or along the lines

diagonals 20.

  Each switching element 22 has two states and is controlled by the second bit of the routing code. When the routing code designates north or south (that is, when the second bit is 0), the switching circuit establishes the

  connection indicated in Figure 6, that is to say, it connects the

  north in each group to the southernmost element in the adjacent group to the north. When the routing code designates east or west (i.e. when the second bit equals 1), the switching circuit establishes the connection shown in Fig. 7, that is, to say that it connects the northernmost element and the southernmost element to the lines

respective diagonals.

  While the switching elements 22 are symbolic

  shown in the accompanying drawings in the form of a

  mechanical devices, they are in practice electronic switches

  classically constructed from known logical components. As shown in FIG. 8, each parity processing element P contains a multiplexer 40 having four inputs 0, 1, 2 and 3 and is controlled by the routing code in the same manner as the multiplexer 16 of FIG. 4. However, in this case, there is no connection with the east and west neighbors. In fact, the input from the south neighbor is connected to inputs O and 3, and the input from the north neighbor is connected

at entries 1 and 2.

  Thus, when the routing code designates the west (11), the parity bits move north within the groups of elements and move along the diagonal lines 20 (due switching shown in Figure 7) between the groups. It can be seen that after eight of

  these trips were made, the content of each group of

  parity processing units moved westwards into

  the adjacent group of parity processing elements, this corre-

  to the westward shift of a datum of one of the sub-

  together 10 (Figure 1) in the adjacent subassembly.

  Similarly, when the routing code denotes the east (01), the parity bits move south within the groups and along the diagonal lines 20 connecting the groups, so that after eight of these displacements, the content of each group of parity processing elements has shifted to

  is in the adjacent group of parity processing elements.

  In summary, we can see that each time a data moves a multiple of eight steps between the elements of

  data processing D, the corresponding parity bits move

  percent between the parity processing elements so as to.

  maintain in the correct relation to the data.

  The data processing elements and the parity processing elements are preferably designed as large scale integrated circuit boards. Conveniently, four processing elements may be incorporated into each large-scale integrated circuit board, so as to form a 2 x 2 part of the assembly. However, it can be seen in FIG. 5 that the parity processing elements must be connected from

  linearly, and not as a two-dimensional set.

  The resolution of this problem is illustrated in Figure 9. This shows two large-scale integrated circuit boards 40 and 42, each containing a 2 x 2 configuration of elements.

  parity processing. The southwestern element of each plate pos-

  A southern connection 44 is connected to the north connection 46 of the northeastern element of the same wafer. In addition, the connection

  south 48 of the southeast element of the upper plate 40 is connected

  at the north 50 connection of the northwestern element of the

  42. This has the effect of bringing together in series the eight

  ments, through their north-south connections to thereby form one of the groups 12 of parity processing elements that

represents Figure 5.

  In U.S. Patent No. 2,020,457, supra, there is described a way of reducing the number of terminals on a large scale integrated circuit wafer, which involves combining adjacent pairs of terminals. The device of the invention could also be implemented by means of platelets having the form described in this patent. Figure 10 shows how two of these pads, 52 and 54, could be connected to produce

  the same effect as that illustrated in Figure 9.

  In the configuration described above, there are different data connections to the routing multiplexers of the data processing elements and the parity processing elements, as shown in FIGS. 4 and 8. However, in the case of implementation by large scale integrated circuits, it would probably be more convenient to make these connections identical, that is to say to do all as shown in Figure 4) and, then, to vary the addresses of issued entry

  routing multiplexers so that the processing elements

  parity receive only the "north" routing codes and

"South".

  According to another variant of the device described above, the assembly could be divided into rectangular subsets, not square. With such a configuration, it is clear that the number of steps required to move the parity bits in the east-west direction between adjacent groups, via the diagonal lines, would be different from the number of steps required to move the data bits. between adjacent subsets. It would therefore be necessary to introduce additional control circuits to disable some of the clock pulses (or to create additional clock pulses) for the parity processing elements during east-west displacements, and , thus, ensure that the parity bits> are maintained in the

  correct relation to the data.

  Of course, those skilled in the art will be able to

  giner, from the devices whose description has just been

  given simply-illustrative and not limiting, various other variations and modifications not out of the box

of the invention.

9 2479508

R E V IN D I C A T I 0 N S

  A data processing device comprising a plurality of processing elements logically arranged in rows and columns, characterized in that each column is divided into several groups (12) of elements, the elements (P) lying within each group (12) being connected together to allow the information to be transferred north and south between adjacent members of the same group,

  and in that it comprises a plurality of switching circuits (22) having

each having two states, o

  (a) in the first state, the switching circuits (22)

  nect the northernmost element (P) in each group (12) to the ele-

  the most southerly in the adjacent group in the northerly direction so as to allow information to be transferred north and south between adjacent groups of the same column, and

  (b) in the second state, the switching circuits (22)

  nect the northernmost element (P) in each group (12) to the ele-

  the most southerly group of the adjacent group in a westerly direction to allow the information to be transferred to the east

  and to the west between adjacent groups of different columns.

  2. Device according to claim 1, characterized in that a routing code having four values representing respectively north, south, east and west is broadcast to all

  the processing elements (P) in parallel.

  3. Device according to claim 2, characterized in that each processing element (P) comprises a selection circuit

  (40) controlled by the routing code to select the information

  coming from its northern neighbor if the routing code represents the south or the east, and the information coming from its southern neighbor if the code

  north or west.

  4. Device according to claim 2 or 3, characterized in that the switching circuits (22) are controlled by the code

  routing so that they are in the first state when

  that the routing code represents north or south, and in the second state when the routing code represents the east or

west.