FR2474227B1 - - Google Patents

Info

Publication number
FR2474227B1
FR2474227B1 FR8001031A FR8001031A FR2474227B1 FR 2474227 B1 FR2474227 B1 FR 2474227B1 FR 8001031 A FR8001031 A FR 8001031A FR 8001031 A FR8001031 A FR 8001031A FR 2474227 B1 FR2474227 B1 FR 2474227B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8001031A
Other languages
French (fr)
Other versions
FR2474227A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CII HONEYWELL BULL
Original Assignee
CII HONEYWELL BULL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CII HONEYWELL BULL filed Critical CII HONEYWELL BULL
Priority to FR8001031A priority Critical patent/FR2474227A1/fr
Priority to DE8181400043T priority patent/DE3163244D1/de
Priority to EP81400043A priority patent/EP0033673B1/fr
Priority to JP584281A priority patent/JPS56105392A/ja
Priority to US06/226,245 priority patent/US4403308A/en
Publication of FR2474227A1 publication Critical patent/FR2474227A1/fr
Application granted granted Critical
Publication of FR2474227B1 publication Critical patent/FR2474227B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
FR8001031A 1980-01-17 1980-01-17 Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant Granted FR2474227A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR8001031A FR2474227A1 (fr) 1980-01-17 1980-01-17 Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant
DE8181400043T DE3163244D1 (en) 1980-01-17 1981-01-14 Mos circuit memory refresh method and corresponding control circuit
EP81400043A EP0033673B1 (fr) 1980-01-17 1981-01-14 Procédé de rafraichissement pour banc de mémoire à circuit "MOS" et séquenceur correspondant
JP584281A JPS56105392A (en) 1980-01-17 1981-01-17 Method of reproducing memory bank and reproducing sequencer
US06/226,245 US4403308A (en) 1980-01-17 1981-01-19 Apparatus for and method of refreshing MOS memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8001031A FR2474227A1 (fr) 1980-01-17 1980-01-17 Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant

Publications (2)

Publication Number Publication Date
FR2474227A1 FR2474227A1 (fr) 1981-07-24
FR2474227B1 true FR2474227B1 (OSRAM) 1983-08-26

Family

ID=9237624

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8001031A Granted FR2474227A1 (fr) 1980-01-17 1980-01-17 Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant

Country Status (5)

Country Link
US (1) US4403308A (OSRAM)
EP (1) EP0033673B1 (OSRAM)
JP (1) JPS56105392A (OSRAM)
DE (1) DE3163244D1 (OSRAM)
FR (1) FR2474227A1 (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567571A (en) * 1982-09-07 1986-01-28 Honeywell Information Systems, Inc. Memory control for refreshing in a step mode
JPS62103898A (ja) * 1985-10-31 1987-05-14 Mitsubishi Electric Corp ダイナミツクランダムアクセスメモリ装置
US4792926A (en) * 1985-12-09 1988-12-20 Kabushiki Kaisha Toshiba High speed memory system for use with a control bus bearing contiguous segmentially intermixed data read and data write request signals
EP0465050B1 (en) * 1990-06-19 1997-09-03 Dell Usa L.P. A digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit
US7043599B1 (en) * 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760379A (en) * 1971-12-29 1973-09-18 Honeywell Inf Systems Apparatus and method for memory refreshment control
US3800295A (en) * 1971-12-30 1974-03-26 Ibm Asynchronously operated memory system
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory
US3790961A (en) * 1972-06-09 1974-02-05 Advanced Memory Syst Inc Random access dynamic semiconductor memory system
US3810129A (en) * 1972-10-19 1974-05-07 Ibm Memory system restoration
IT1002272B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di ricarica in memoria a semiconduttori
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
JPS5255337A (en) * 1975-10-31 1977-05-06 Hitachi Ltd Refresh control system
US4040122A (en) * 1976-04-07 1977-08-02 Burroughs Corporation Method and apparatus for refreshing a dynamic memory by sequential transparent readings
US4172282A (en) * 1976-10-29 1979-10-23 International Business Machines Corporation Processor controlled memory refresh
US4185323A (en) * 1978-07-20 1980-01-22 Honeywell Information Systems Inc. Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
US4238842A (en) * 1978-12-26 1980-12-09 Ibm Corporation LARAM Memory with reordered selection sequence for refresh

Also Published As

Publication number Publication date
JPS56105392A (en) 1981-08-21
EP0033673A2 (fr) 1981-08-12
EP0033673B1 (fr) 1984-04-25
DE3163244D1 (en) 1984-05-30
FR2474227A1 (fr) 1981-07-24
EP0033673A3 (en) 1981-08-19
US4403308A (en) 1983-09-06

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Legal Events

Date Code Title Description
ST Notification of lapse