FR2466141A1 - CIRCUIT SUITABLE FOR SYNCHRONIZING THE RECEIVING SECTION OF A MODULE, OF A LAND INTERFACE OF THE DIGITAL VOICE INTERPOLATION TYPE, APPLICABLE PARTICULARLY TO AN AMRT SATELLITE TRANSMISSION SYSTEM (MULTIPLE ACCESS BY TIME DISTRIBUTION) - Google Patents

Abstract

CIRCUIT SUITABLE FOR SYNCHRONIZING THE RECEIVING SECTION OF A DIGITAL VOICE INTERPOLATION TERRESTRIAL INTERFACE MODULE, PARTICULARLY APPLICABLE TO A TIME DIVISION SATELLITE TRANSMISSION SYSTEM INCLUDING A PLURALITY OF STATIONS. THE COUNTING OF THE NUMBER OF NORMAL CHANNELS AND THE NUMBER OF OVERLOADED CHANNELS ISSUED BY EACH STATION IS MADE BY MEANS OF A SINGLE COUNTING CHAIN TO WHICH IS ASSOCIATED A MEMORY CAPABLE OF MEMORIZING THE CHANNELS THAT WERE ISSUED BY EACH STATION. IF A GENERIC STATION EMITS OTHER CHANNEL BLOCKS IN THE SAME FRAME, IN THE COUNTING CHAIN THE NUMBER OF CHANNELS STORED PREVIOUSLY IS PRELOADED AND THE COUNTING CONTINUES FROM THIS NUMBER.

Description

The present invention relates to a circuit capable of

  synchronize the receiving section of an interface module

  terrestrial, of the digital voice interpolation type, applicable

  particularly with regard to a time division satellite transmission system comprising a plurality of stations. A transmission system of this type is indicated in the specific technique by the acronym AMRT (multiple access

by time distribution).

  Each station is constituted by a central unit to which a plurality of terrestrial interface modules are connected, which are shaped in relation to the type of

  signal they receive as input. Some of the information modules

  terrestrial surface receiving digital signals as input

  are generally of the voice interpolation type to increase

  ter the operation of satellite channels.

  The principle on which the interpolation of the voice is based is indeed the use of the idle times, present in a telephone conversation, to send on the same

  transmission channel conversations from other parties

their.

  The terrestrial interface modules must adapt the data flow received to the requirements of the TDMA system and memorize the data flow which they have developed in order to allow it to be read at a higher speed from the said unit.

central.

  The latter places this data in the packet of the transmitting station in a pre-established position of the TDMA frame.

  which has a duration of 750 p sec.

  In the receiving section of the land interface module

  The data is written at high speed and in packets and is read continuously in order to create the

  digital stream to be sent directly to the ter lines

  restres. In cases where, in the same TDMA frame, the module

  of the terrestrial interface in question must receive pro-

  coming from the same station in two or more time intervals separated by the transmission of other stations, some problems arise with regard to the synchronization of

  data write operations.

  In fact, the distribution of the channels inside the frame can be such that at the receiving station x channels from station A arrive, which could be followed by y channels from station B, then from z channels coming again from the

station A and so on.

  A first technical solution which enables correct writing operations to be carried out consists in providing for the presence of as many channel counters as there are stations.

  whose terrestrial interface module can receive data.

  In this way the channel counter associated with the sta-

  tion A, after counting said x channels, stops to resume

  dre the counting of the z successive channels, once the counter associated with station B has counted the y channels, from the

position where it stopped.

  A solution of this type requires the presence of a large number of counting chains which, when the number of stations to be received is high, have a significant influence on the cost and on

  the size of the terrestrial interface module.

  The object of the present invention is to produce a particularly simple and economical circuit which does not

  not having the above-mentioned drawback.

  For this purpose, the invention provides for the presence of a single counting chain with which is associated a memory capable of memorizing the number of channels which have been switched on by each station; if in the same frame a generic station transmits another block of channels the counting chain is preloaded with the number of

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  previously memorized channels and counting continues from

of that number.

  The circuit according to the invention therefore provides for the presence in combination of the following characteristic elements: - counting means, supplied by a sequence of synchronization pulses drawn by said central unit

  of the data packet received from the satellite, capable of counting the name-

  bre of channels reaching the terrestrial interface module; - memory means, comprising as many areas of

  memory that there are stations whose interface module lands-

  being in question can receive data, capable of memorizing the number of channels provided by said counting means; resetting means able to zero at the start of each frame both said counting means and said memory means; - control means, supplied with a number w of pulses emitted by the central unit with a code expressing the code of the originating station, capable of making available a first sequence of pulses intended to be used to render said memory means capable of memorizing the number written in said counting means, proper. Other to make available a second sequence of pulses characterized by the presence of a pulse at the height of the pulse w / 2 of the sequence which they receive as input and finally suitable for making available as output a third sequence of pulses intended to be used to authorize the transfer of the contents of the memory area, identified by said call sign of the origin station,

  in the cells of said counting means.

  Other features of the invention will result

  more clearly on reading the following description

  to a nonlimiting example of embodiment and with reference to the attached figures in which:

  - Figure 1 shows the block diagram of an information module

  terrestrial terface of the type with digital interpolation of the voice, FIG. 2 shows the block diagram of a circuit produced according to the invention placed in the unit CR

of figure 1.

  Figure 3 shows waveforms related to the

figure 2.

  The terrestrial interface module of FIG. 1 comprises a transmitting section ST, a receiving section SR, and an interface unit UI to which N PCM systems terminate (for example

2 M bits / sec.).

  The transmitting section provides for the presence of SD voice developers which make it possible to detect if in the different channels

  of said PCM systems there is a phonic activity.

  An AC channel allocation unit has been connected to the SD unit, which associates the terrestrial channel, in which, at a generic instant, the SD unit has detected the presence of sound activity, to a previous satellite channel associated with another terrestrial channel in which the SD unit does not detect the presence of a

phonic activity.

  The channel allocation unit AC also makes it possible to communicate, to an AM unit responsible for forming the message.

  of attribution, the satellite-terrestrial channel association -

  previously performed and it also allows to write this as-

  association in a memory CT transmission connections capable of memorizing all the associations of the satellite channels with the channels

  carried out by the AC unit.

  Since SD voice developers introduce a delay in the detection of phonic activity, the presence has been foreseen

  a DL delay line capable of delaying the PCM codes which must

  may be transmitted in order to compensate for the delays introduced

by the SD unit.

  At the output of the DL unit there is provided a memory for

  pressure MC comprising a first memory A and a second memory B. After having written continuously six PCM frames in memory A the six successive frames are written in memory B and, at the same time, the reading of the memory A. The reading is carried out at a high speed, emitting a data packet, respecting the satellite channel-terrestrial channel association memorized by the CT unit; suppose

  the AC unit has associated the terrestrial channel 20 with the satellite channel

  lite 15; when the satellite channel 15 must be transmitted, it is the data written to line 20 of memory A or else of memory B of MC, which is in the reading phase, which

are read.

  At the output of the compression memory MC, provision has been made

  an adder circuit CS able to associate the attribute message

  tion, codified by the AM unit according to an error correction code

  reur, to the data packet which corresponds to the output of the MC unit. The data packet with its allocation message

  is sent to said central unit (in the specific technique

  that this unit is indicated by the acronym CTTE) which is responsible for modulating it and sending it to the satellite, to which

  in addition the data transmitted by the other stations.

  Satellite retransmits transmitted data packets

  by all stations at each of the central units, which

  transmit them to the receiving section of the inter-

land face.

  Each receiving station SR provides for the presence of a decoder of the allocation message DM, to which is connected a memory reception connections CR into which the content of the allocation message is poured in order to inform the receiving section on the associations

  satellite channel-terrestrial channel carried out by the transmitting section

  this from the terrestrial interface module belonging to the station which

  sent the received data packet.

  The CR memory includes as many memory units as there are stations from which it is possible to receive data (max. 30) and each unit has as many memory lines as there are satellite channels (120 + 17) suitable for use

  by a generic terrestrial interface module. -

  Data reaches ME expansion memory

  which also provides for the presence of a memory A and a memory-

  re B; in the time interval o in a generic memory are performed the write operations at high speed and in packets, in the other memory it is the read operations which are carried out continuously, at the speed of

  PCM systems exiting the terrestrial interface module.

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  The circuit which is the subject of the invention provides for the presence of means for counting the satellite channels, the outputs of which are used to perform the reading by

  the memory receive connections CR.

  In particular, the central unit makes the station code available, which will also be called origin by the

  suite, which issued a generic data packet and this indication

  tif addresses the memory unit associated with this station; the outputs of said counting means, on the other hand, address the memory line o the number of the terrestrial channel is memorized

  that has been associated with each satellite channel.

  If we refer to the previous example o the terrestrial channel 20 is associated with the satellite channel 15, when said counting means address line 15 of the memory unit associated with the station to which this channel relates, c 'is the

number 20 which is read.

  When the data relating to satellite channel 15 appear at the input of the memory ME, these are stored in line 20 of memory A or else of memory B which is

in the writing phase.

  Since a generic SR receiving section can receive

  data during several programs interspersed with

  from other stations, the circuit following the

  vention provides for the presence of a cupboard presenting as many

  res that there are stations from which it can receive data; in these areas is written the number of channels received during previous broadcasts in order to resume counting at

from that number.

  The circuit according to the invention illustrated in FIG. 3 in fact provides for the presence of counting means CN comprising a first counter CN1, supplied by a sequence of synchronization pulses CK available at the output of the central unit, which extracts this sequence of data packets received from the satellite: the unit CN1 has the counting capacity 24, equal to the

  number of bits provided in each channel of the TDMA frame.

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  Once the CN1 unit has counted 24 pulses from the CO sequence, it outputs a pulse which reaches the input of 2 = pDage of a second counter CN2 with the counting capacity 120, equal to the maximum number of uui satellite channels can be operated by the terrestrial interface module. Since all the seven channels are normal, an overloaded channel can be provided, the pulses which correspond to the output of the CNI unit also reach a third counter CN3, with counting capacity seven, the excitation of which at the output causes the advancement of a fourth counter CN4, having a counting capacity 17, equal to the maximum number of overload channels provided. At the end of the second, third and fourth

  counter, cn has provided memory means MM comprising the meta

  random access memories RAM1, RAM2 and RAM3 each of which

  presents 3rd Line equal to the maximum number of stations that can

  can be reviewed by the terrestrial interface module.

  The random access memories are sent by the confi-

  bnanire guration expressing the code of the station of origin, which is provided by the central unit, which receives the data

  stations following a pre-established sequence.

  Origire reaches memories through as many mul-

  tiplexers!., T1 E2 and MT3 who receive on their second

  inputs the binary configuration available at the output of a

  third counter B5, with a counting capacity of 30,

  being part of AZ reset means.

  These zero AZ delivery means further include three

  other MT4, MT5 and MT6 multiplexers, the first group of which

  trées is connected to the output of their random access memory and

  on the second group of inputs to which we applied

  impulses with logic level zero.

  The ^! Ts rultiplexers output the pre-

  the first group of inputs or the codes present in the second group of inputs, depending on the logic level present

a control signal.

  In addition, provision has been made for the presence of control means MA comprising a sixth counter CN6 having a capacity of

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  count eight, equal to the number of "ready" pulses supplied by the central unit; at the output of the unit CN6 there is provided a decoding unit DC capable of exciting a first output at the height of a pulse (for example the 3rd) of the first half of the "ready" interval capable of exciting a second exit

  at the height of the central impulse (4th impulse) of the

  tervalle "ready" and able to excite a third outing at the top

  impulse (for example the 7th) of the second half

of this interval.

  O We will now explain the operation of the circuit structure which has just been illustrated, using the

waveforms in Figure 3.

  In diagram a of FIG. 3 two are shown

  pulses which define a time interval of 750 P sec.

equal to an TDMA frame.

  In diagram b, on the other hand, an im-

  pulse which is at the start of the frame and which defines a time interval intended to be used to perform the

  reset operations using said AZ means; this impulse

  sion does indeed reach the control input of the multiplexers MT1, ..., MT6 causing the emission of the codes present on their

second group of inputs.

  At the same time the counter CN2 is made suitable for counting, after which it progressively scans all the addresses of the memories RAM1, RAM2 and RAM3, while in the counters CN2, CN3 and CN4 are charged with pulses presenting the level

logic zero.

  In the presence of each address scanned by the CN5 unit, the pulses with zero logic level, available at the

  output of said counters CN2, CN3 and CN4, are memorized, provo-

  as for resetting either said counters or all

  lines of random access memories.

  Once the reset phase is complete, the multiplexers MT1,

  .., MT6 make available the ..DTD: codes present on said first group of inputs.

  From this moment the central unit provides in ef-

  fet the original call sign 1 of the first station like this

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  is illustrated in diagram c, with a package of eight pulses

  "Loan" as shown in diagram d. At the first output of the DOC unit are available the pulses represented in the diagram e intended to be used to write in the memories with casual access the contents of the counting means, at the second output are available the pulses f intended to be sent to a transcoding unit TR, while

  that at the third output the pulses represented

  shown in diagram g intended to be used for auto-

  riser the loading of codes in the counters CN2, CN3 and CN.

  Origin 1 is transcoded by the unit TR into a code belonging to the terrestrial interface module and the transcoded code is memorized, for a time interval not less than

  the appearance of the pulse of the sequence f relating to the inter-

  valle "loan" associated with the successive origin, as it is il-

glossy in diagram h.

  Once the issuance of "ready" pulses rela-

  tives to a generic station is finished, the central unit returns

  Di data available, as illustrated in the slide

  gram i, issued by the station whose original code is

  available at the output of the MT1, MT2 and MT3 units.

  This data is organized into channels of 24 bits each and a generic terrestrial interface module can process 120

  normal channels as well as 17 overload channels; central unit

  extracts from these data the synchronization pulses CK which arrive at the unit CN1, which excites its own output at the

end of each channel.

  The pulses which correspond to the output of the unit CN1 arrive at the counter CN2, which consequently counts the normal channels, and they also arrive at the counter CN5, with which the counter CN4 which counts is cascaded,

  therefore, the overload channels.

  Once the count of the channels relative to the origin

   1 is complete, the pulse of the sequence e succeeding the origi-

  does that which we have just considered causes the transfer of the content

  said counters in the memories RAM1, RAM2 and RAM3 respectively.

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  --erenz and in particular in the lines identified by the origin

: ranscoded Ot1.

  At the height of the pulse of the sequence f succeeding - the imulsicn of the sequence e indicated above, the unit TR prevents the emission of the code Ot1 and makes available the code Ot2 re-atif at the origin 02 This Ot2 code addresses the successive line of the random access memories in which, according to the example considered, bits with a logic level zero are stored which, at the height of the pulse of the sequence g succeeding

  appearance of the Ot2 origin, are transferred to the cel-

! of the counters CN2, CN3 and CN4.

  If in the same frame the origin 02 had previously put a number h of normal channels and a number k, y of overload channels, in the lines of memories RAM1, RAM2 and RAI.:3

  addressed by the code Ot2, it would be the number f, y and k respec-

i -: ement which would be memorized.

  In this case the impulse of said sequence g would have created VouZ ie loading of the numbers h, y and k in the cells

  CN2, CN3 and CN4 counters whose coiptage would therefore

  Duent continued from these numbers. If we assume that during the second emission, the origin 02 emits hi1, Yl and k1 channels, the numbers h + hi and y + y, and k + k1 present in the

  counters CN2, CN3 and CN4 at the end of this transmission will be trans-

  in the corresponding row of the RAM1, RAM2 and RAM3 sections at the height of the pulse of the sequence e following the appearance of this origin and so on in the case where other programs are recorded on the part from the origin 02 it is thus possible, by means of the random access memories RAM1,

  RA2 and RAM3, to use a single counting chain to perform

  To correctly read the operations of reading the number of the terrestrial channel, associated with each satellite channel, written in the memory

  Figure 2 CR in accordance with the stated goal.

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Claims (6)

  1. Circuit capable of synchronizing the receiving section   a terrestrial interface module, of the digital interpolation type   voice risk, particularly applicable to a satellite transmission system comprising a plurality of stations, each of which is constituted by a central unit to which a plurality of terrestrial interface modules are connected, characterized in that it comprises counting means (CN), supplied by a sequence of synchronization pulses (CK) drawn by said central unit from the received data packet   of the satellite, able to count the number of channels reaching   relate to the interface module in question; memory means   (MM), comprising as many memory lines as there are sta-   the terrestrial interface module in question can re-   receiving data, capable of storing the number of channels provided by said counting means; zero offset means (AZ) capable of zeroing at the start of each frame both said counting means (CN) and said memory means (MM); control means (MA), supplied with a number w of "ready" pulses (d) emitted by the central unit with a code expressing the code of the originating station, capable of making a first sequence available of pulses (e) intended to be used to make said memory means (MM) capable of memorizing the number written in said counting means (CN), further capable of outputting a second sequence of pulses characterized by presence of an impulse coinciding with the impulse w / 2 of the sequence which they receive as input and finally suitable for making available at output a third sequence 2466141 1   of pulses (g) intended to be used to authorize the transfer of the content of the memory line identified by said original code in the cells of said counting means (CN). 2. Circuit according to claim 1, characterized in that said counting means comprise a first   counter (CN1) with a counting capacity equal to the name-   bre of pulses provided in a channel, the excitation of which at the output includes the advancement of a second and a-, third counter (CN2 and CN3) having a counting capacity equal to the maximum number of channels which can be operated by the terrestrial interface module, respectively equal to the number of normal channels located between two consecutive overload channels, further characterized by the fact that the excitation of the   output by the third counter involves the advancement of a   third counter (CN4) with equal counting capacity   the maximum number of overload channels provided.   3. Circuit according to claim 1, characterized by   the fact that said memory means (MM) comprise a pre-   second, a second and a third random access memory (RAM1, RAM2 and RAM3) to the data input of which is connected the output of said second, said third and said fourth counter   (CN2, CN3 and ON4) respectively and at the input of the addresses of-   what is the said origin station code supplied by the central unit.   4. Circuit according to claims 1 and 3 characterized   by the fact that said code from the originating station reaches the random access memories (RAM1, RAM2 and RAM3) by means of a transcoding unit (TR) which supplies the first group of inputs with a first, d 'a second and a third multiplexer (MT1, MT2 and MT3) which receive on the second group-of inputs the outputs of a fifth counter (CN5) forming part of said means derernise- z' ro (AZ) and having a counting capacity equal to the number of lines provided in said random access memories, by the fact that the outputs of the random access memories (RAM1, RAM2 and RAM3) arrive at the input respectively at a fourth, at a fifth and at a sixth multiplexer (MT4, 2466141 I   MT5 and MT6) to the second group of inputs from which pulses having a logic level of zero arrive, and thereby   that the exits of the fourth, fifth and sixth multiple-   xer (MT4, MT5 and MT6) arrive at input to said second, to said third and to said fourth counter (CN2, CN3 and CN4) respectively. 5. Circuit according to claim 1, characterized by   the fact that said control means (MA) comprise a sixth-   me counter (CN6), with a counting capacity equal to the number of "ready" pulses it receives at the input, at the output   which is provided with a decoding unit (DC) having a pre-   first output to which said first printing sequence corresponds   drives (e), further having a second outlet on which   is available said second pulse sequence (f) and pre-   also feeling a third output to which corresponds said third sequence of pulses (g), further characterized by the fact that each pulse of said first sequence (e),   or else of said third sequence (g) coincides with an im-   pre-established drive of the first, or the second half,   of each of the "ready" pulse packets.   6. Circuit according to claim 5, characterized in that said transcoding unit (TR) is capable of converting the code Oi of the origin station into a code Ot1 of the terrestrial interface module and that it is in furthermore capable of making the transcoded code available at output for a time interval not less than the appearance of a pulse of said second sequence (f) relating to the pulse packet of   "loan" associated with the origin 0. + 1. i