FR2451600A1 - Systeme de traitement de donnees a dispositif d'interconnexion de processeurs multiples - Google Patents

Systeme de traitement de donnees a dispositif d'interconnexion de processeurs multiples

Info

Publication number
FR2451600A1
FR2451600A1 FR8005574A FR8005574A FR2451600A1 FR 2451600 A1 FR2451600 A1 FR 2451600A1 FR 8005574 A FR8005574 A FR 8005574A FR 8005574 A FR8005574 A FR 8005574A FR 2451600 A1 FR2451600 A1 FR 2451600A1
Authority
FR
France
Prior art keywords
data processing
interconnection device
processing system
multiple processor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8005574A
Other languages
English (en)
Other versions
FR2451600B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of FR2451600A1 publication Critical patent/FR2451600A1/fr
Application granted granted Critical
Publication of FR2451600B1 publication Critical patent/FR2451600B1/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

L'INVENTION CONCERNE UN SYSTEME DE TRAITEMENT DE DONNEES DANS LEQUEL IL EST PREVU PLUSIEURS UNITES DE TRAITEMENT DE DONNEES10, 10A ET UN DISPOSITIF D'INTERCONNEXION14. DANS CE SYSTEME, UNE PREMIERE UNITE DE TRAITEMENT DE DONNEES10 COMPORTE UN MOYEN POUR EMETTRE DES INSTRUCTIONS COMPRENANT UNE INSTRUCTION DE VERROUILLAGE ET UNE INSTRUCTION DE DEVERROUILLAGE; CHAQUE UNITE DE TRAITEMENT DE DONNEES COMPREND DES MOYENS DE COMMUTATION REAGISSANT AUX INSTRUCTIONS DE MANIERE QUE, LORSQUE LA PREMIERE UNITE DE TRAITEMENT DE DONNEES10 EMET UNE INSTRUCTION DE VERROUILLAGE, DES UNITES DE TRAITEMENT DE DONNEES10A... AUTRES QUE LA PREMIERE SOIENT EMPECHEES DE TRANSFERER UNE INFORMATION PAR LE DISPOSITIF D'INTERCONNEXION14 EN MEME TEMPS QU'UNE INSTRUCTION DE VERROUILLAGE JUSQU'A CE QU'UNE INSTRUCTION DE DEVERROUILLAGE SOIT EMISE PAR UNE UNITE DE TRAITEMENT DE DONNEES. APPLICATION AUX ORDINATEURS.
FR8005574A 1979-03-12 1980-03-12 Systeme de traitement de donnees a dispositif d'interconnexion de processeurs multiples Expired FR2451600B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1935079A 1979-03-12 1979-03-12

Publications (2)

Publication Number Publication Date
FR2451600A1 true FR2451600A1 (fr) 1980-10-10
FR2451600B1 FR2451600B1 (fr) 1987-03-20

Family

ID=21792732

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8005574A Expired FR2451600B1 (fr) 1979-03-12 1980-03-12 Systeme de traitement de donnees a dispositif d'interconnexion de processeurs multiples

Country Status (5)

Country Link
JP (1) JPS55134470A (fr)
CA (1) CA1143854A (fr)
DE (1) DE3009530A1 (fr)
FR (1) FR2451600B1 (fr)
GB (1) GB2044499B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381542A (en) * 1980-10-20 1983-04-26 Digital Equipment Corporation System for interrupt arbitration
DE3126384C2 (de) * 1981-07-03 1983-04-21 Siemens AG, 1000 Berlin und 8000 München Prioritätsauswahleinrichtung
US4719567A (en) * 1982-04-29 1988-01-12 Motorola, Inc. Method and apparatus for limiting bus utilization
AU564271B2 (en) * 1983-09-22 1987-08-06 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system
US4941083A (en) * 1987-05-01 1990-07-10 Digital Equipment Corporation Method and apparatus for initiating interlock read transactions on a multiprocessor computer system
US5341510A (en) * 1987-05-01 1994-08-23 Digital Equipment Corporation Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
EP0397778B1 (fr) * 1988-01-27 1995-12-13 Storage Technology Corporation Procede et appareil a mode de mise en route sans retard
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
JPH02306355A (ja) * 1988-10-25 1990-12-19 Apollo Computer Inc バスロックシステム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815099A (en) * 1970-04-01 1974-06-04 Digital Equipment Corp Data processing system
FR2213537A1 (fr) * 1973-01-08 1974-08-02 Philips Nv
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815099A (en) * 1970-04-01 1974-06-04 Digital Equipment Corp Data processing system
FR2213537A1 (fr) * 1973-01-08 1974-08-02 Philips Nv
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources

Also Published As

Publication number Publication date
JPS55134470A (en) 1980-10-20
CA1143854A (fr) 1983-03-29
DE3009530A1 (de) 1980-09-25
JPS6119062B2 (fr) 1986-05-15
GB2044499A (en) 1980-10-15
DE3009530C2 (fr) 1990-06-13
FR2451600B1 (fr) 1987-03-20
GB2044499B (en) 1983-11-16

Similar Documents

Publication Publication Date Title
FR2451600A1 (fr) Systeme de traitement de donnees a dispositif d'interconnexion de processeurs multiples
ES8308107A1 (es) "una instalacion de tratamiento de informacion para realizar operaciones de tratamiento de datos".
EP0346128A3 (fr) Méthode et système pour accomplir des taches de raisonnement par propositions en utilisant des pocesseurs en parallèle.
JPS533755A (en) Goods sales management system
FR2286438A1 (fr) Dispositif de selection de micro-instructions dans un systeme de traitement de donnees
ES8500536A1 (es) Un dispositivo indicador de telefono relativo a los costes de llamadas
JPS5345949A (en) Arithmetic unit for n-point discrete fourier conversion
Zimmerman Liturgy as language of faith a liturgical methodology in the mode of Paul Ricoeur's textual hermeneutics.
EP0009488A1 (fr) Dispositif de mesure du rapport entre un nombre d'evenements consecutifs d'une premiere serie d'evenements et d'une seconde serie d'evenements.
JPS53137643A (en) Managing system for hospital information
FR2408870A1 (fr) Procede et dispositif pour la multiplication d'une valeur stochastique par un coefficient plus grand que l'unite
JPS5326632A (en) Common memory control unit
Neumann Risks to the public
JPS53109448A (en) Information processor
JPS5271147A (en) Common panel control system for data processing unit
JPS5437644A (en) Information processing system
FR2451601A1 (fr) Systeme de traitement de donnees a processeurs multiples
FR2457046A1 (fr) Appareil autonome d'appel automatique par reseau commute pour systeme de traitement d'informations
FR2372474A1 (fr) Systeme pour l'apprentissage de l'utilisation d'un microcalculateur
JPS5282051A (en) Payment system in cash
BAKER Efficient multiple processor coordination[Final Report, Oct. 1974- Nov. 1976]
JPS5341298A (en) Vending machine for deferred payment system
JPS5434640A (en) Memory unit
Yasaki Personal link.
JPS5321534A (en) Information processor

Legal Events

Date Code Title Description
ST Notification of lapse