FR2445090A1 - METHOD FOR MANUFACTURING PRINTED CIRCUITS - Google Patents

METHOD FOR MANUFACTURING PRINTED CIRCUITS

Info

Publication number
FR2445090A1
FR2445090A1 FR7931102A FR7931102A FR2445090A1 FR 2445090 A1 FR2445090 A1 FR 2445090A1 FR 7931102 A FR7931102 A FR 7931102A FR 7931102 A FR7931102 A FR 7931102A FR 2445090 A1 FR2445090 A1 FR 2445090A1
Authority
FR
France
Prior art keywords
pattern
resin
printed circuits
substrate
manufacturing printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7931102A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of FR2445090A1 publication Critical patent/FR2445090A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09581—Applying an insulating coating on the walls of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Abstract

Le procédé de fabrication de circuits imprimés selon la présente invention comprend les étapes suivantes : dépôt d'un motif sur un substrat isolant, ce motif étant constitué d'une résine époxy chargée à l'argent, l'immersion du substrat avec son motif dans un bain de placage en cuivre non électrolytique, puis le traitement du substrat plaqué de façon à consolider le motif revêtu de cuivre sur celui-ci. De préférence, la résine époxy est une résine bisphénol A avec un agent de durcissement aromatique chargé de particules de paillettes d'argent ayant un diamètre compris entre 20 et 50 microns. Une telle résine peut être préparée avec une consistance permettant son utilisation dans un procédé d'impression à écran de soie.The method of manufacturing printed circuits according to the present invention comprises the following steps: depositing a pattern on an insulating substrate, this pattern consisting of an epoxy resin charged with silver, immersing the substrate with its pattern in a non-electrolytic copper plating bath, then treating the plated substrate so as to consolidate the copper coated pattern thereon. Preferably, the epoxy resin is a bisphenol A resin with an aromatic curing agent loaded with silver flake particles having a diameter of between 20 and 50 microns. Such a resin can be prepared with a consistency permitting its use in a silk screen printing process.

FR7931102A 1978-12-19 1979-12-19 METHOD FOR MANUFACTURING PRINTED CIRCUITS Withdrawn FR2445090A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7849056A GB2038101B (en) 1978-12-19 1978-12-19 Printed circuits

Publications (1)

Publication Number Publication Date
FR2445090A1 true FR2445090A1 (en) 1980-07-18

Family

ID=10501809

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7931102A Withdrawn FR2445090A1 (en) 1978-12-19 1979-12-19 METHOD FOR MANUFACTURING PRINTED CIRCUITS

Country Status (3)

Country Link
ES (1) ES487017A1 (en)
FR (1) FR2445090A1 (en)
GB (1) GB2038101B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG109432A1 (en) * 1999-09-27 2005-03-30 Sony Corp Printed wiring board and display apparatus

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2172436B (en) * 1985-03-16 1989-06-21 Marconi Electronic Devices Electrical circuit
GB2172438A (en) * 1985-03-16 1986-09-17 Marconi Electronic Devices Printed circuits
GB2172439B (en) * 1985-03-16 1989-06-21 Marconi Electronic Devices Electrical circuit
GB2172437A (en) * 1985-03-16 1986-09-17 Marconi Electronic Devices Printed circuits
US4812353A (en) * 1986-12-27 1989-03-14 Sankyo Kasei Kabushiki Kaisha Process for the production of circuit board and the like
KR900005308B1 (en) * 1987-12-31 1990-07-27 정풍물산 주식회사 Printed circuit board method
GB8928640D0 (en) * 1989-12-19 1990-02-21 Technology Applic Company Limi Electrical conductors of conductive resin

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB749621A (en) * 1950-08-28 1956-05-30 John Albert Chitty Improvements in the manufacture of electrically conductive elements or coatings
FR1237098A (en) * 1959-01-08 1960-07-22 Photocircuits Corp Circuit board forming process
US3259559A (en) * 1962-08-22 1966-07-05 Day Company Method for electroless copper plating
GB1075007A (en) * 1964-10-16 1967-07-12 Photocircuits Corp Products produced by chemical metallization
US3745045A (en) * 1971-01-06 1973-07-10 R Brenneman Electrical contact surface using an ink containing a plating catalyst

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB749621A (en) * 1950-08-28 1956-05-30 John Albert Chitty Improvements in the manufacture of electrically conductive elements or coatings
FR1237098A (en) * 1959-01-08 1960-07-22 Photocircuits Corp Circuit board forming process
US3259559A (en) * 1962-08-22 1966-07-05 Day Company Method for electroless copper plating
GB1075007A (en) * 1964-10-16 1967-07-12 Photocircuits Corp Products produced by chemical metallization
US3745045A (en) * 1971-01-06 1973-07-10 R Brenneman Electrical contact surface using an ink containing a plating catalyst

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 15, no. 5, octobre 1972, NEW YORK (US) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG109432A1 (en) * 1999-09-27 2005-03-30 Sony Corp Printed wiring board and display apparatus
US7417867B1 (en) 1999-09-27 2008-08-26 Sony Corporation Printed wiring board and display apparatus

Also Published As

Publication number Publication date
GB2038101A (en) 1980-07-16
ES487017A1 (en) 1980-09-16
GB2038101B (en) 1983-02-09

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Legal Events

Date Code Title Description
ST Notification of lapse