FR2423029A1 - Dispositif memoire - Google Patents
Dispositif memoireInfo
- Publication number
- FR2423029A1 FR2423029A1 FR7909130A FR7909130A FR2423029A1 FR 2423029 A1 FR2423029 A1 FR 2423029A1 FR 7909130 A FR7909130 A FR 7909130A FR 7909130 A FR7909130 A FR 7909130A FR 2423029 A1 FR2423029 A1 FR 2423029A1
- Authority
- FR
- France
- Prior art keywords
- pulses
- memory device
- counter circuit
- predetermined number
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
- H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
Abstract
Un dispositif mémoire 10 comporte une première et une seconde bornes d'accès C0 , F0 qui fournissent tous les signaux opérationnels ainsi que les signaux d'alimentation et de masse. Des impulsions de synchromsation appliquées à la première borne C0 sont comptées par un compteur 52 et lorsque trois impulsions de synchronisation ont été comptées, un signal de sortie commande des transistors 24, 30 pour connecter les bornes d'accès C0 , F0 aux bornes d'entrée de masse et d'alimentation d'un dispositif d'alimentation interne 20. A d'autres moments, les bornes d'accès C0 , F0 sont connectées, par l'intermédiaire des transistors 12, 32 à des circuits récepteurs de données et générateurs de signaux de synchronisation à l'intérieur du dispositif mémoire. Dans une variante de réalisation, le compteur 52 est remplacé par un détecteur à seuil qui fonctionne lorsque l'importance de la différence entre les signaux d'entrée appliqués aux bornes d'accès C0 , F0 dépasse une valeur prédéterminée.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/895,329 US4148099A (en) | 1978-04-11 | 1978-04-11 | Memory device having a minimum number of pins |
US05/895,328 US4145760A (en) | 1978-04-11 | 1978-04-11 | Memory device having a reduced number of pins |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2423029A1 true FR2423029A1 (fr) | 1979-11-09 |
FR2423029B1 FR2423029B1 (fr) | 1982-06-18 |
Family
ID=27129109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7909130A Granted FR2423029A1 (fr) | 1978-04-11 | 1979-04-11 | Dispositif memoire |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2423029A1 (fr) |
NL (1) | NL7902352A (fr) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3691538A (en) * | 1971-06-01 | 1972-09-12 | Ncr Co | Serial read-out memory system |
US3851221A (en) * | 1972-11-30 | 1974-11-26 | P Beaulieu | Integrated circuit package |
-
1979
- 1979-03-26 NL NL7902352A patent/NL7902352A/xx not_active Application Discontinuation
- 1979-04-11 FR FR7909130A patent/FR2423029A1/fr active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3691538A (en) * | 1971-06-01 | 1972-09-12 | Ncr Co | Serial read-out memory system |
US3851221A (en) * | 1972-11-30 | 1974-11-26 | P Beaulieu | Integrated circuit package |
Non-Patent Citations (1)
Title |
---|
EXBK/71 * |
Also Published As
Publication number | Publication date |
---|---|
NL7902352A (nl) | 1979-10-15 |
FR2423029B1 (fr) | 1982-06-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |