FR2423029A1 - Dispositif memoire - Google Patents

Dispositif memoire

Info

Publication number
FR2423029A1
FR2423029A1 FR7909130A FR7909130A FR2423029A1 FR 2423029 A1 FR2423029 A1 FR 2423029A1 FR 7909130 A FR7909130 A FR 7909130A FR 7909130 A FR7909130 A FR 7909130A FR 2423029 A1 FR2423029 A1 FR 2423029A1
Authority
FR
France
Prior art keywords
pulses
memory device
counter circuit
predetermined number
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7909130A
Other languages
English (en)
Other versions
FR2423029B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/895,329 external-priority patent/US4148099A/en
Priority claimed from US05/895,328 external-priority patent/US4145760A/en
Application filed by NCR Corp filed Critical NCR Corp
Publication of FR2423029A1 publication Critical patent/FR2423029A1/fr
Application granted granted Critical
Publication of FR2423029B1 publication Critical patent/FR2423029B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Un dispositif mémoire 10 comporte une première et une seconde bornes d'accès C0 , F0 qui fournissent tous les signaux opérationnels ainsi que les signaux d'alimentation et de masse. Des impulsions de synchromsation appliquées à la première borne C0 sont comptées par un compteur 52 et lorsque trois impulsions de synchronisation ont été comptées, un signal de sortie commande des transistors 24, 30 pour connecter les bornes d'accès C0 , F0 aux bornes d'entrée de masse et d'alimentation d'un dispositif d'alimentation interne 20. A d'autres moments, les bornes d'accès C0 , F0 sont connectées, par l'intermédiaire des transistors 12, 32 à des circuits récepteurs de données et générateurs de signaux de synchronisation à l'intérieur du dispositif mémoire. Dans une variante de réalisation, le compteur 52 est remplacé par un détecteur à seuil qui fonctionne lorsque l'importance de la différence entre les signaux d'entrée appliqués aux bornes d'accès C0 , F0 dépasse une valeur prédéterminée.
FR7909130A 1978-04-11 1979-04-11 Dispositif memoire Granted FR2423029A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/895,329 US4148099A (en) 1978-04-11 1978-04-11 Memory device having a minimum number of pins
US05/895,328 US4145760A (en) 1978-04-11 1978-04-11 Memory device having a reduced number of pins

Publications (2)

Publication Number Publication Date
FR2423029A1 true FR2423029A1 (fr) 1979-11-09
FR2423029B1 FR2423029B1 (fr) 1982-06-18

Family

ID=27129109

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7909130A Granted FR2423029A1 (fr) 1978-04-11 1979-04-11 Dispositif memoire

Country Status (2)

Country Link
FR (1) FR2423029A1 (fr)
NL (1) NL7902352A (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691538A (en) * 1971-06-01 1972-09-12 Ncr Co Serial read-out memory system
US3851221A (en) * 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691538A (en) * 1971-06-01 1972-09-12 Ncr Co Serial read-out memory system
US3851221A (en) * 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/71 *

Also Published As

Publication number Publication date
NL7902352A (nl) 1979-10-15
FR2423029B1 (fr) 1982-06-18

Similar Documents

Publication Publication Date Title
US4365174A (en) Pulse counter type circuit for power-up indication
ES8405218A1 (es) Circuito para reajustar un circuito logico digital
JPS5437462A (en) Complementary mos circuit device
JPS57117184A (en) Non-volatile memory circuit for portable electronic device
FR2423029A1 (fr) Dispositif memoire
EP0049462A3 (fr) Dispositif de mémoire
JPS5585156A (en) Protective unit of transmission system
GB1074027A (en) Signal detection system
JPS57140029A (en) Output circuit
GB1195141A (en) Improvements in or relating to Digit Storage and Transmission Means.
GB924203A (en) Improvements in memory elements
JPS5341111A (en) Dial signal sending device
GB1471563A (en) Output retaining electronic circuit
GB865298A (en) Improvements in and relating to pulse generators
JPS5730189A (en) Ic memory device
JPS5374847A (en) Memory unit
JPS56135285A (en) White level tracking circuit
SU1273923A1 (ru) Генератор импульсов со случайной длительностью
JPS57116401A (en) Frequency multiplying circuit
JPH0631995B2 (ja) チャイム音発生装置
JPS56102145A (en) Data transmission system
JPS56155434A (en) Receiving circuit for switch closing signal
JPS53138250A (en) Output buffer circuit
JPS54122080A (en) Chattering eliminator circuit
JPS57154960A (en) Demodulating circuit

Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse