FR2389967A1 - - Google Patents

Info

Publication number
FR2389967A1
FR2389967A1 FR7813748A FR7813748A FR2389967A1 FR 2389967 A1 FR2389967 A1 FR 2389967A1 FR 7813748 A FR7813748 A FR 7813748A FR 7813748 A FR7813748 A FR 7813748A FR 2389967 A1 FR2389967 A1 FR 2389967A1
Authority
FR
France
Prior art keywords
memory
main memory
modified
buffer memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7813748A
Other languages
English (en)
Other versions
FR2389967B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2389967A1 publication Critical patent/FR2389967A1/fr
Application granted granted Critical
Publication of FR2389967B1 publication Critical patent/FR2389967B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

Système de mémoires hiérarchisées comportant une mémoire-tampon entre la mémoire principale et le dispositif de traitement de données. L'adresse 10 des données modifiées à écrire en mémoire principale est comparée dans 24 aux adresses 26 des positions de mémoire principale modifiées par des sources autres que la mémoire-tampon 16. Suivant le résultat de la comparaison un emmagasinage partiel ou total est effectué utilisant un nouveau mot de données dans 20. L'invention permet d'accroître les performances des systèmes de mémoire.
FR7813748A 1977-05-05 1978-04-05 Expired FR2389967B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/794,323 US4157586A (en) 1977-05-05 1977-05-05 Technique for performing partial stores in store-thru memory configuration

Publications (2)

Publication Number Publication Date
FR2389967A1 true FR2389967A1 (fr) 1978-12-01
FR2389967B1 FR2389967B1 (fr) 1980-06-13

Family

ID=25162322

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7813748A Expired FR2389967B1 (fr) 1977-05-05 1978-04-05

Country Status (5)

Country Link
US (1) US4157586A (fr)
JP (1) JPS53137638A (fr)
DE (1) DE2817431C2 (fr)
FR (1) FR2389967B1 (fr)
GB (1) GB1552574A (fr)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2811318C2 (de) * 1978-03-16 1983-02-17 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Übertragung und Speicherung eines Teilwortes
US4290105A (en) * 1979-04-02 1981-09-15 American Newspaper Publishers Association Method and apparatus for testing membership in a set through hash coding with allowable errors
DE3068498D1 (en) * 1979-05-09 1984-08-16 Int Computers Ltd Hierarchical data storage system
CA1187198A (fr) * 1981-06-15 1985-05-14 Takashi Chiba Systeme pour controler l'acces a un tampon de canaux
US4571674A (en) * 1982-09-27 1986-02-18 International Business Machines Corporation Peripheral storage system having multiple data transfer rates
US4561051A (en) * 1984-02-10 1985-12-24 Prime Computer, Inc. Memory access method and apparatus in multiple processor systems
US4680702A (en) * 1984-04-27 1987-07-14 Honeywell Information Systems Inc. Merge control apparatus for a store into cache of a data processing system
US4896259A (en) * 1984-09-07 1990-01-23 International Business Machines Corporation Apparatus for storing modifying data prior to selectively storing data to be modified into a register
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4875155A (en) * 1985-06-28 1989-10-17 International Business Machines Corporation Peripheral subsystem having read/write cache with record access
DE68917326T2 (de) * 1988-01-20 1995-03-02 Advanced Micro Devices Inc Organisation eines integrierten Cachespeichers zur flexiblen Anwendung zur Unterstützung von Multiprozessor-Operationen.
US4918695A (en) * 1988-08-30 1990-04-17 Unisys Corporation Failure detection for partial write operations for memories
US5214777A (en) * 1989-03-27 1993-05-25 Ncr Corporation High speed read/modify/write memory system and method
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
JP3637054B2 (ja) * 1989-09-11 2005-04-06 エルジー・エレクトロニクス・インコーポレーテッド キャッシュ／メインメモリのコンシステンシを維持するための装置及び方法
EP0470737A1 (fr) * 1990-08-06 1992-02-12 NCR International, Inc. Procédé de fonctionnement et structure d'une antémémoire
US5420994A (en) * 1990-08-06 1995-05-30 Ncr Corp. Method for reading a multiple byte data element in a memory system with at least one cache and a main memory
US5287512A (en) * 1990-08-06 1994-02-15 Ncr Corporation Computer memory system and method for cleaning data elements
US5357622A (en) * 1990-09-27 1994-10-18 Dell U.S.A., L.P. Apparatus for queing and storing data writes into valid word patterns
US5522065A (en) * 1991-08-30 1996-05-28 Compaq Computer Corporation Method for performing write operations in a parity fault tolerant disk array
US5530835A (en) * 1991-09-18 1996-06-25 Ncr Corporation Computer memory data merging technique for computers with write-back caches
US5333305A (en) * 1991-12-27 1994-07-26 Compaq Computer Corporation Method for improving partial stripe write performance in disk array subsystems
US5666515A (en) * 1993-02-18 1997-09-09 Unisys Corporation Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
US5530948A (en) * 1993-12-30 1996-06-25 International Business Machines Corporation System and method for command queuing on raid levels 4 and 5 parity drives
US5809228A (en) * 1995-12-27 1998-09-15 Intel Corporaiton Method and apparatus for combining multiple writes to a memory resource utilizing a write buffer
US6629168B1 (en) * 2000-06-15 2003-09-30 Hewlett-Packard Development Company, Lp. Byte-swapping for efficient use of memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
US3984818A (en) * 1974-02-09 1976-10-05 U.S. Philips Corporation Paging in hierarchical memory systems

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
US3786427A (en) * 1971-06-29 1974-01-15 Ibm Dynamic address translation reversed

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
US3984818A (en) * 1974-02-09 1976-10-05 U.S. Philips Corporation Paging in hierarchical memory systems

Also Published As

Publication number Publication date
DE2817431A1 (de) 1978-11-09
FR2389967B1 (fr) 1980-06-13
JPS53137638A (en) 1978-12-01
US4157586A (en) 1979-06-05
DE2817431C2 (de) 1986-06-26
GB1552574A (en) 1979-09-12

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