FR2375659A1 - Microprocessor system with bus and clock control - has unidirectional bus linking arithmetic and logic unit to output buffer - Google Patents

Microprocessor system with bus and clock control - has unidirectional bus linking arithmetic and logic unit to output buffer

Info

Publication number
FR2375659A1
FR2375659A1 FR7735659A FR7735659A FR2375659A1 FR 2375659 A1 FR2375659 A1 FR 2375659A1 FR 7735659 A FR7735659 A FR 7735659A FR 7735659 A FR7735659 A FR 7735659A FR 2375659 A1 FR2375659 A1 FR 2375659A1
Authority
FR
France
Prior art keywords
bus
arithmetic
logic unit
output buffer
clock control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7735659A
Other languages
French (fr)
Other versions
FR2375659B1 (en
Inventor
Edward D Finnegan
George B Marenin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/754,193 external-priority patent/US4181934A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2375659A1 publication Critical patent/FR2375659A1/en
Application granted granted Critical
Publication of FR2375659B1 publication Critical patent/FR2375659B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

A microprocessor architecture for a microprocessor on a single semiconducting chip has an improved bus system and clock control for internal operation management. These enable reductions in the number of drive circuits, the power consumption, and the number of connections per chip. A unidirectional bus connects the arithmetic and logic unit to an output buffer via a full register. An address register connected to the bus controls address modification or branching and connection operations. Also connected to the bus are registers for accumulation, accumulator expansion, errors, interrupts, counter, and current operations. An instruction decoder instigates data or instruction signal storage. A multiplex access channel and priority encoder manage cycle associations and interrupt requests. Controllers select input and output channels.
FR7735659A 1976-12-27 1977-11-18 Microprocessor system with bus and clock control - has unidirectional bus linking arithmetic and logic unit to output buffer Granted FR2375659A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75446276A 1976-12-27 1976-12-27
US05/754,193 US4181934A (en) 1976-12-27 1976-12-27 Microprocessor architecture with integrated interrupts and cycle steals prioritized channel

Publications (2)

Publication Number Publication Date
FR2375659A1 true FR2375659A1 (en) 1978-07-21
FR2375659B1 FR2375659B1 (en) 1981-09-11

Family

ID=27115887

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7735659A Granted FR2375659A1 (en) 1976-12-27 1977-11-18 Microprocessor system with bus and clock control - has unidirectional bus linking arithmetic and logic unit to output buffer

Country Status (3)

Country Link
FR (1) FR2375659A1 (en)
IT (1) IT1114938B (en)
NL (1) NL7714230A (en)

Also Published As

Publication number Publication date
NL7714230A (en) 1978-06-29
FR2375659B1 (en) 1981-09-11
IT1114938B (en) 1986-02-03

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