FR2352340A1 - Appareil de reconfiguration automatique pour processeur d'entree/sortie - Google Patents

Appareil de reconfiguration automatique pour processeur d'entree/sortie

Info

Publication number
FR2352340A1
FR2352340A1 FR7714561A FR7714561A FR2352340A1 FR 2352340 A1 FR2352340 A1 FR 2352340A1 FR 7714561 A FR7714561 A FR 7714561A FR 7714561 A FR7714561 A FR 7714561A FR 2352340 A1 FR2352340 A1 FR 2352340A1
Authority
FR
France
Prior art keywords
input
output processor
reconfiguration device
automatic reconfiguration
automatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7714561A
Other languages
English (en)
Other versions
FR2352340B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2352340A1 publication Critical patent/FR2352340A1/fr
Application granted granted Critical
Publication of FR2352340B1 publication Critical patent/FR2352340B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
FR7714561A 1976-05-17 1977-05-12 Appareil de reconfiguration automatique pour processeur d'entree/sortie Granted FR2352340A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/686,975 US4070704A (en) 1976-05-17 1976-05-17 Automatic reconfiguration apparatus for input/output processor

Publications (2)

Publication Number Publication Date
FR2352340A1 true FR2352340A1 (fr) 1977-12-16
FR2352340B1 FR2352340B1 (fr) 1983-04-01

Family

ID=24758514

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7714561A Granted FR2352340A1 (fr) 1976-05-17 1977-05-12 Appareil de reconfiguration automatique pour processeur d'entree/sortie

Country Status (7)

Country Link
US (1) US4070704A (fr)
JP (1) JPS6027048B2 (fr)
AU (1) AU505184B2 (fr)
BE (1) BE854710A (fr)
CA (1) CA1095630A (fr)
DE (1) DE2721319C2 (fr)
FR (1) FR2352340A1 (fr)

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FR2655750A1 (fr) * 1989-12-11 1991-06-14 Bretagne Occidentale Brest Uni Systeme de traitement de donnees multiprocesseur a bus actif reconfigurable.

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US4803623A (en) * 1986-10-31 1989-02-07 Honeywell Bull Inc. Universal peripheral controller self-configuring bootloadable ramware
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JP2522778B2 (ja) * 1987-01-20 1996-08-07 能美防災株式会社 防災装置
US5038320A (en) * 1987-03-13 1991-08-06 International Business Machines Corp. Computer system with automatic initialization of pluggable option cards
EP0289779A3 (fr) * 1987-04-07 1990-08-22 Siemens Nixdorf Informationssysteme Aktiengesellschaft Processus d'identification initiale et de mise à jour de l'identification des modules d'un ordinateur à disponibilité élevée
US5155833A (en) * 1987-05-11 1992-10-13 At&T Bell Laboratories Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
US4970640A (en) * 1987-08-28 1990-11-13 International Business Machines Corporation Device initiated partial system quiescing
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US5257387A (en) * 1988-09-09 1993-10-26 Compaq Computer Corporation Computer implemented method and apparatus for dynamic and automatic configuration of a computer system and circuit boards including computer resource allocation conflict resolution
US5450570A (en) * 1988-09-09 1995-09-12 Compaq Computer Corp. Computer implemented method and apparatus for dynamic configuration of a computer system and circuit boards including computer resource allocation conflict resolution
US5353432A (en) * 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
US5263148A (en) * 1988-09-09 1993-11-16 Compaq Computer Corporation Method and apparatus for configuration of computer system and circuit boards
GB8823510D0 (en) * 1988-10-06 1988-11-16 Int Computers Ltd Data processing system
US5163145A (en) * 1989-04-25 1992-11-10 Dell Usa L.P. Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference
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US5212785A (en) * 1990-04-06 1993-05-18 Micro Technology, Inc. Apparatus and method for controlling data flow between a computer and memory devices
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US5432927A (en) * 1992-06-17 1995-07-11 Eaton Corporation Fail-safe EEPROM based rewritable boot system
US5574914A (en) * 1993-01-04 1996-11-12 Unisys Corporation Method and apparatus for performing system resource partitioning
CA2126950A1 (fr) * 1993-07-30 1995-01-31 Bryan M. Willman Amorcage d'un ordinateur au moyen du dernier ensemble de donnees de configuration exact connu
US20030088611A1 (en) * 1994-01-19 2003-05-08 Mti Technology Corporation Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
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JPH0844552A (ja) * 1994-08-01 1996-02-16 Fujitsu Ltd 個人の言語による問題むき補助計算装置のためのプログラム作成システム
US5623610A (en) * 1994-10-31 1997-04-22 Intel Corporation System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
US5742847A (en) * 1994-10-31 1998-04-21 Intel Corporation M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions
US5615404A (en) * 1994-10-31 1997-03-25 Intel Corporation System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals
US5621901A (en) * 1994-10-31 1997-04-15 Intel Corporation Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other
BR9509458A (pt) * 1994-10-31 1998-01-06 Intel Corp M&A para permutar dados estado e comandos sobre uma montagem serial hierárquica usando pacotes de comunicação
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US6279098B1 (en) 1996-12-16 2001-08-21 Unisys Corporation Method of and apparatus for serial dynamic system partitioning
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
GB2332541B (en) 1997-12-20 2002-12-04 Ibm Boot failure recovery system and method
US6212631B1 (en) * 1999-01-15 2001-04-03 Dell Usa, L.P. Method and apparatus for automatic L2 cache ECC configuration in a computer system
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US8542574B2 (en) * 2005-06-29 2013-09-24 Honeywell International Inc. Apparatus and method for network error prevention
KR100915395B1 (ko) * 2008-03-28 2009-09-03 동양건설(주) 각도조절 및 충격흡수가 가능한 도로용 울타리
US8819484B2 (en) 2011-10-07 2014-08-26 International Business Machines Corporation Dynamically reconfiguring a primary processor identity within a multi-processor socket server
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2184656A1 (fr) * 1972-05-12 1973-12-28 Burroughs Corp
US3818199A (en) * 1971-09-30 1974-06-18 G Grossmann Method and apparatus for processing errors in a data processing unit
US4014005A (en) * 1976-01-05 1977-03-22 International Business Machines Corporation Configuration and control unit for a heterogeneous multi-system

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US3386082A (en) * 1965-06-02 1968-05-28 Ibm Configuration control in multiprocessors
SE313849B (fr) * 1966-03-25 1969-08-25 Ericsson Telefon Ab L M
BE755034A (fr) * 1969-08-19 1971-02-19 Siemens Ag Installation de traitement d'informations a commande centrale programmepar memoire
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818199A (en) * 1971-09-30 1974-06-18 G Grossmann Method and apparatus for processing errors in a data processing unit
FR2184656A1 (fr) * 1972-05-12 1973-12-28 Burroughs Corp
US4014005A (en) * 1976-01-05 1977-03-22 International Business Machines Corporation Configuration and control unit for a heterogeneous multi-system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2655750A1 (fr) * 1989-12-11 1991-06-14 Bretagne Occidentale Brest Uni Systeme de traitement de donnees multiprocesseur a bus actif reconfigurable.
EP0433142A1 (fr) * 1989-12-11 1991-06-19 Universite De Bretagne Occidentale, ( Brest) Système de traitement de données multiprocesseur à bus actif reconfigurable

Also Published As

Publication number Publication date
AU505184B2 (en) 1979-11-08
JPS6027048B2 (ja) 1985-06-27
DE2721319A1 (de) 1977-12-01
DE2721319C2 (de) 1985-08-22
BE854710A (fr) 1977-09-16
CA1095630A (fr) 1981-02-10
FR2352340B1 (fr) 1983-04-01
JPS52140245A (en) 1977-11-22
AU2448077A (en) 1978-10-26
US4070704A (en) 1978-01-24

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