FR2344071B1 - - Google Patents
Info
- Publication number
- FR2344071B1 FR2344071B1 FR7706720A FR7706720A FR2344071B1 FR 2344071 B1 FR2344071 B1 FR 2344071B1 FR 7706720 A FR7706720 A FR 7706720A FR 7706720 A FR7706720 A FR 7706720A FR 2344071 B1 FR2344071 B1 FR 2344071B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4921—Single digit adding or subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4924—Digit-parallel adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US66446076A | 1976-03-08 | 1976-03-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2344071A1 FR2344071A1 (fr) | 1977-10-07 |
| FR2344071B1 true FR2344071B1 (US08124317-20120228-C00026.png) | 1981-10-02 |
Family
ID=24666056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7706720A Granted FR2344071A1 (fr) | 1976-03-08 | 1977-03-08 | Procede et dispositif pour executer selectivement une addition binaire ou une addition bcd |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS52108745A (US08124317-20120228-C00026.png) |
| DE (1) | DE2708637C3 (US08124317-20120228-C00026.png) |
| FR (1) | FR2344071A1 (US08124317-20120228-C00026.png) |
| GB (1) | GB1525893A (US08124317-20120228-C00026.png) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0525492Y2 (US08124317-20120228-C00026.png) * | 1987-01-26 | 1993-06-28 | ||
| JPH09231055A (ja) * | 1996-02-27 | 1997-09-05 | Denso Corp | 論理演算回路及びキャリールックアヘッド加算器 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3112396A (en) * | 1957-05-03 | 1963-11-26 | Ibm | Arithmetic circuitry |
| US3711693A (en) * | 1971-06-30 | 1973-01-16 | Honeywell Inf Systems | Modular bcd and binary arithmetic and logical system |
-
1977
- 1977-01-28 GB GB363277A patent/GB1525893A/en not_active Expired
- 1977-02-28 DE DE19772708637 patent/DE2708637C3/de not_active Expired
- 1977-03-08 JP JP2451877A patent/JPS52108745A/ja active Granted
- 1977-03-08 FR FR7706720A patent/FR2344071A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5534454B2 (US08124317-20120228-C00026.png) | 1980-09-06 |
| DE2708637A1 (de) | 1977-09-15 |
| FR2344071A1 (fr) | 1977-10-07 |
| DE2708637C3 (de) | 1985-07-18 |
| DE2708637B2 (de) | 1980-06-19 |
| GB1525893A (en) | 1978-09-20 |
| JPS52108745A (en) | 1977-09-12 |
