FR2342585B1 - - Google Patents

Info

Publication number
FR2342585B1
FR2342585B1 FR7705611A FR7705611A FR2342585B1 FR 2342585 B1 FR2342585 B1 FR 2342585B1 FR 7705611 A FR7705611 A FR 7705611A FR 7705611 A FR7705611 A FR 7705611A FR 2342585 B1 FR2342585 B1 FR 2342585B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7705611A
Other languages
French (fr)
Other versions
FR2342585A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of FR2342585A1 publication Critical patent/FR2342585A1/en
Application granted granted Critical
Publication of FR2342585B1 publication Critical patent/FR2342585B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
FR7705611A 1976-02-28 1977-02-25 Polyphase MOSFET circuit for pulse duration variations - uses ring counters with decoders connected to RS flip flop controlled by digital signal applied to AND gates Granted FR2342585A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19762608265 DE2608265C2 (en) 1976-02-28 1976-02-28 Polyphase MOS circuit for changing the pulse duration

Publications (2)

Publication Number Publication Date
FR2342585A1 FR2342585A1 (en) 1977-09-23
FR2342585B1 true FR2342585B1 (en) 1982-04-02

Family

ID=5971171

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7705611A Granted FR2342585A1 (en) 1976-02-28 1977-02-25 Polyphase MOSFET circuit for pulse duration variations - uses ring counters with decoders connected to RS flip flop controlled by digital signal applied to AND gates

Country Status (4)

Country Link
JP (1) JPS5931894B2 (en)
DE (1) DE2608265C2 (en)
FR (1) FR2342585A1 (en)
IT (1) IT1078248B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2753453C2 (en) * 1977-11-30 1982-01-28 Siemens AG, 1000 Berlin und 8000 München Digital frequency divider
JPS6025929B2 (en) * 1978-01-25 1985-06-21 ソニー株式会社 PWM modulation circuit
US4441037A (en) * 1980-12-22 1984-04-03 Burroughs Corporation Internally gated variable pulsewidth clock generator
DE3126747C2 (en) * 1981-07-01 1983-06-01 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Circuit arrangement for adapting the length of incoming pulses
US4818894A (en) * 1987-03-09 1989-04-04 Hughes Aircraft Company Method and apparatus for obtaining high frequency resolution of a low frequency signal
US5293628A (en) * 1991-11-04 1994-03-08 Motorola, Inc. Data processing system which generates a waveform with improved pulse width resolution
US5530298A (en) * 1993-09-03 1996-06-25 Dresser Industries, Inc. Solid-state pulse generator
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
DE102011080110B4 (en) * 2011-07-29 2018-10-31 Siemens Aktiengesellschaft Method for generating a clock signal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440546A (en) * 1965-11-15 1969-04-22 Ibm Variable period and pulse width delay line pulse generating system

Also Published As

Publication number Publication date
DE2608265B1 (en) 1977-09-08
IT1078248B (en) 1985-05-08
FR2342585A1 (en) 1977-09-23
JPS5931894B2 (en) 1984-08-04
JPS52119053A (en) 1977-10-06
DE2608265C2 (en) 1978-04-27

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Legal Events

Date Code Title Description
ST Notification of lapse