FR2340622B1 - - Google Patents
Info
- Publication number
- FR2340622B1 FR2340622B1 FR7700642A FR7700642A FR2340622B1 FR 2340622 B1 FR2340622 B1 FR 2340622B1 FR 7700642 A FR7700642 A FR 7700642A FR 7700642 A FR7700642 A FR 7700642A FR 2340622 B1 FR2340622 B1 FR 2340622B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/656,756 US4075045A (en) | 1976-02-09 | 1976-02-09 | Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps |
| US05/702,247 US4085498A (en) | 1976-02-09 | 1976-07-02 | Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2340622A1 FR2340622A1 (fr) | 1977-09-02 |
| FR2340622B1 true FR2340622B1 (en:Method) | 1980-10-24 |
Family
ID=27097257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7700642A Granted FR2340622A1 (fr) | 1976-02-09 | 1977-01-05 | Procede de fabrication d'un transistor a effet de champ a grille au silicium et d'un condensateur; cellule ainsi obtenue |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2340622A1 (en:Method) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2842545C2 (de) * | 1978-09-29 | 1980-07-31 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Halbleiterspeicher mit Depletion-Varaktoren als Speicherkondensatoren |
-
1977
- 1977-01-05 FR FR7700642A patent/FR2340622A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2340622A1 (fr) | 1977-09-02 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |