FR2334247B1 - - Google Patents
Info
- Publication number
- FR2334247B1 FR2334247B1 FR7632293A FR7632293A FR2334247B1 FR 2334247 B1 FR2334247 B1 FR 2334247B1 FR 7632293 A FR7632293 A FR 7632293A FR 7632293 A FR7632293 A FR 7632293A FR 2334247 B1 FR2334247 B1 FR 2334247B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with electro-magnetic coupling of the control current
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S505/00—Superconductor technology: apparatus, material, process
- Y10S505/825—Apparatus per se, device per se, or process of making or operating same
- Y10S505/856—Electrical transmission or interconnection system
- Y10S505/857—Nonlinear solid-state device system or circuit
- Y10S505/858—Digital logic
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/636,868 US4039856A (en) | 1975-12-02 | 1975-12-02 | Distributed josephson junction logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2334247A1 FR2334247A1 (fr) | 1977-07-01 |
| FR2334247B1 true FR2334247B1 (OSRAM) | 1978-12-15 |
Family
ID=24553675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7632293A Granted FR2334247A1 (fr) | 1975-12-02 | 1976-10-21 | Circuit logique a plusieurs jonctions josephson |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4039856A (OSRAM) |
| JP (1) | JPS5268354A (OSRAM) |
| DE (1) | DE2651603C3 (OSRAM) |
| FR (1) | FR2334247A1 (OSRAM) |
| GB (1) | GB1560678A (OSRAM) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4360898A (en) * | 1980-06-30 | 1982-11-23 | International Business Machines Corporation | Programmable logic array system incorporating Josephson devices |
| US4344052A (en) * | 1980-09-29 | 1982-08-10 | International Business Machines Corporation | Distributed array of Josephson devices with coherence |
| US4633439A (en) * | 1982-07-21 | 1986-12-30 | Hitachi, Ltd. | Superconducting read-only memories or programable logic arrays having the same |
| US4733182A (en) * | 1986-03-25 | 1988-03-22 | The United States Of America As Represented By The United States Department Of Energy | Josephson junction Q-spoiler |
| US5233244A (en) * | 1991-03-25 | 1993-08-03 | Fujitsu Limited | Josephson logic gate having a plurality of input ports and a josephson logic circuit that uses such a josephson logic gate |
| EP0999654B1 (en) * | 1998-11-06 | 2005-03-30 | Matsushita Electric Industrial Co., Ltd. | Receiver and signal transmission system |
| JP4524126B2 (ja) * | 2004-03-09 | 2010-08-11 | 富士通株式会社 | 超電導sfq回路 |
| US7129870B2 (en) * | 2003-08-29 | 2006-10-31 | Fujitsu Limited | Superconducting latch driver circuit generating sufficient output voltage and pulse-width |
| US7615385B2 (en) | 2006-09-20 | 2009-11-10 | Hypres, Inc | Double-masking technique for increasing fabrication yield in superconducting electronics |
| US10769344B1 (en) * | 2019-07-22 | 2020-09-08 | Microsoft Technology Licensing, Llc | Determining timing paths and reconciling topology in a superconducting circuit design |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3458735A (en) * | 1966-01-24 | 1969-07-29 | Gen Electric | Superconductive totalizer or analog-to-digital converter |
| CH559481A5 (OSRAM) * | 1973-12-13 | 1975-02-28 | Ibm |
-
1975
- 1975-12-02 US US05/636,868 patent/US4039856A/en not_active Expired - Lifetime
-
1976
- 1976-10-21 FR FR7632293A patent/FR2334247A1/fr active Granted
- 1976-11-03 GB GB45670/76A patent/GB1560678A/en not_active Expired
- 1976-11-12 DE DE2651603A patent/DE2651603C3/de not_active Expired
- 1976-11-15 JP JP51136453A patent/JPS5268354A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE2651603B2 (de) | 1978-08-17 |
| DE2651603C3 (de) | 1979-04-19 |
| DE2651603A1 (de) | 1977-06-08 |
| FR2334247A1 (fr) | 1977-07-01 |
| GB1560678A (en) | 1980-02-06 |
| JPS5268354A (en) | 1977-06-07 |
| US4039856A (en) | 1977-08-02 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |