FR2305784A1 - Dispositif de multiplication - Google Patents

Dispositif de multiplication

Info

Publication number
FR2305784A1
FR2305784A1 FR7608740A FR7608740A FR2305784A1 FR 2305784 A1 FR2305784 A1 FR 2305784A1 FR 7608740 A FR7608740 A FR 7608740A FR 7608740 A FR7608740 A FR 7608740A FR 2305784 A1 FR2305784 A1 FR 2305784A1
Authority
FR
France
Prior art keywords
multiplication device
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7608740A
Other languages
English (en)
Other versions
FR2305784B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INSTITUT MATEMATIKI I MEKHANIKI
Original Assignee
INSTITUT MATEMATIKI I MEKHANIKI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INSTITUT MATEMATIKI I MEKHANIKI filed Critical INSTITUT MATEMATIKI I MEKHANIKI
Publication of FR2305784A1 publication Critical patent/FR2305784A1/fr
Application granted granted Critical
Publication of FR2305784B1 publication Critical patent/FR2305784B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR7608740A 1975-03-25 1976-03-25 Dispositif de multiplication Granted FR2305784A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU7502114928A SU579618A1 (ru) 1975-03-25 1975-03-25 Устройство дл умножени

Publications (2)

Publication Number Publication Date
FR2305784A1 true FR2305784A1 (fr) 1976-10-22
FR2305784B1 FR2305784B1 (fr) 1979-02-02

Family

ID=20613182

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7608740A Granted FR2305784A1 (fr) 1975-03-25 1976-03-25 Dispositif de multiplication

Country Status (5)

Country Link
US (1) US4064400A (fr)
DE (1) DE2612750A1 (fr)
FR (1) FR2305784A1 (fr)
GB (1) GB1519095A (fr)
SU (1) SU579618A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3138698A1 (de) * 1981-09-29 1983-04-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zur potenzierung grosser binaerzahlen in einer restklasse modulo n, insbesondere zur verschluesselung und entschluesselung digital dargestellter nachrichten

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334277A (en) * 1977-09-28 1982-06-08 The United States Of America As Represented By The Secretary Of The Navy High-accuracy multipliers using analog and digital components
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
JPS6042965B2 (ja) * 1979-06-01 1985-09-26 愛介 片山 複数法形高速乗算装置
US4816805A (en) * 1987-02-02 1989-03-28 Grumman Aerospace Corporation Residue number system shift accumulator decoder
US5010505A (en) * 1987-02-27 1991-04-23 The Boeing Company Optical cross bar arithmetic/logic unit
US4948959A (en) * 1988-07-15 1990-08-14 The Boeing Company Optical computer including pipelined conversion of numbers to residue representation
US4939682A (en) * 1988-07-15 1990-07-03 The Boeing Company Integrated electro-optic arithmetic/logic unit and method for making the same
US4910699A (en) * 1988-08-18 1990-03-20 The Boeing Company Optical computer including parallel residue to binary conversion
US5050120A (en) * 1989-09-29 1991-09-17 The Boeing Company Residue addition overflow detection processor
US5107451A (en) * 1990-01-30 1992-04-21 The Boeing Company Method and apparatus for pipelined detection of overflow in residue arithmetic multiplication
US5033016A (en) * 1990-03-06 1991-07-16 The Boeing Company Coherence multiplexed arithmetic/logic unit
US6356636B1 (en) * 1998-07-22 2002-03-12 Motorola, Inc. Circuit and method for fast modular multiplication
US6690315B1 (en) * 2003-01-31 2004-02-10 United States Of America As Represented By The Secretary Of The Air Force Quadbit kernel function algorithm and receiver
US7440989B1 (en) 2004-04-02 2008-10-21 The United States Of America As Represented By The Secretary Of The Air Force Kernel function approximation and receiver

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH412411A (de) * 1959-12-30 1966-04-30 Ibm Vorrichtung zur Durchführung von Multiplikationen und Divisionen im Zahlensystem der Restklassen
BE620229A (fr) * 1961-07-19

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEANT *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3138698A1 (de) * 1981-09-29 1983-04-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zur potenzierung grosser binaerzahlen in einer restklasse modulo n, insbesondere zur verschluesselung und entschluesselung digital dargestellter nachrichten

Also Published As

Publication number Publication date
DE2612750A1 (de) 1976-10-07
US4064400A (en) 1977-12-20
SU579618A1 (ru) 1977-11-05
FR2305784B1 (fr) 1979-02-02
GB1519095A (en) 1978-07-26

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Legal Events

Date Code Title Description
ST Notification of lapse