FR2193256A1 - - Google Patents

Info

Publication number
FR2193256A1
FR2193256A1 FR7325991A FR7325991A FR2193256A1 FR 2193256 A1 FR2193256 A1 FR 2193256A1 FR 7325991 A FR7325991 A FR 7325991A FR 7325991 A FR7325991 A FR 7325991A FR 2193256 A1 FR2193256 A1 FR 2193256A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7325991A
Other languages
French (fr)
Other versions
FR2193256B1 (pl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of FR2193256A1 publication Critical patent/FR2193256A1/fr
Application granted granted Critical
Publication of FR2193256B1 publication Critical patent/FR2193256B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
FR7325991A 1972-07-17 1973-07-16 Expired FR2193256B1 (pl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27251972A 1972-07-17 1972-07-17

Publications (2)

Publication Number Publication Date
FR2193256A1 true FR2193256A1 (pl) 1974-02-15
FR2193256B1 FR2193256B1 (pl) 1978-02-17

Family

ID=23040144

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7325991A Expired FR2193256B1 (pl) 1972-07-17 1973-07-16

Country Status (4)

Country Link
JP (1) JPS4963966A (pl)
FR (1) FR2193256B1 (pl)
GB (1) GB1404524A (pl)
NL (1) NL7309531A (pl)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2937993A1 (de) * 1979-09-20 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-halbleiterschaltungen nach der silizium-gate-technologie
US7790624B2 (en) 2008-07-16 2010-09-07 Global Foundries Inc. Methods for removing a metal-comprising material from a semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3507766A (en) * 1968-01-19 1970-04-21 Texas Instruments Inc Method of forming a heterogeneous composite insulating layer of silicon dioxide in multilevel integrated circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEANT *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2937993A1 (de) * 1979-09-20 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-halbleiterschaltungen nach der silizium-gate-technologie
US7790624B2 (en) 2008-07-16 2010-09-07 Global Foundries Inc. Methods for removing a metal-comprising material from a semiconductor substrate

Also Published As

Publication number Publication date
DE2334213B2 (de) 1974-08-29
JPS4963966A (pl) 1974-06-20
NL7309531A (pl) 1974-01-21
FR2193256B1 (pl) 1978-02-17
DE2334213A1 (de) 1974-01-31
GB1404524A (en) 1975-09-03

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Legal Events

Date Code Title Description
ST Notification of lapse