FR2161895A1 - - Google Patents

Info

Publication number
FR2161895A1
FR2161895A1 FR7231236A FR7231236A FR2161895A1 FR 2161895 A1 FR2161895 A1 FR 2161895A1 FR 7231236 A FR7231236 A FR 7231236A FR 7231236 A FR7231236 A FR 7231236A FR 2161895 A1 FR2161895 A1 FR 2161895A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7231236A
Other languages
French (fr)
Other versions
FR2161895B1 (en:Method
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
North American Rockwell Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by North American Rockwell Corp filed Critical North American Rockwell Corp
Publication of FR2161895A1 publication Critical patent/FR2161895A1/fr
Application granted granted Critical
Publication of FR2161895B1 publication Critical patent/FR2161895B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR7231236A 1971-12-02 1972-09-04 Expired FR2161895B1 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20424671A 1971-12-02 1971-12-02

Publications (2)

Publication Number Publication Date
FR2161895A1 true FR2161895A1 (en:Method) 1973-07-13
FR2161895B1 FR2161895B1 (en:Method) 1975-03-07

Family

ID=22757184

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7231236A Expired FR2161895B1 (en:Method) 1971-12-02 1972-09-04

Country Status (5)

Country Link
US (1) US3745370A (en:Method)
JP (1) JPS528143B2 (en:Method)
CA (1) CA945227A (en:Method)
FR (1) FR2161895B1 (en:Method)
GB (1) GB1340020A (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0022266A1 (en) * 1979-07-10 1981-01-14 Kabushiki Kaisha Toshiba Semiconductor circuit device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2131939C3 (de) * 1971-06-26 1975-11-27 Ibm Deutschland Gmbh, 7000 Stuttgart Logisch gesteuerte Inverterstufe
US4449224A (en) * 1980-12-29 1984-05-15 Eliyahou Harari Dynamic merged load logic (MLL) and merged load memory (MLM)
CN116722861B (zh) * 2023-08-09 2023-11-14 脉冲视觉(北京)科技有限公司 信号的逻辑处理方法、装置、电子设备和存储介质

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3502909A (en) * 1968-12-10 1970-03-24 Shell Oil Co Pulsed substrate transistor inverter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3502909A (en) * 1968-12-10 1970-03-24 Shell Oil Co Pulsed substrate transistor inverter

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
*REVUE FRANCAISE "ELECTRONIQUEET MICROELECTRIQUE INDUSTRIELLES", NO. 46, SEPTEMBRE 1971, "VERS DES LOGIQUES MOS AUSSI RAPIDES QUE LES BIPOLAIRES", H. LILEN, PAGES 17-27.) *
REVUE AMERICAINE "IBM TECHNICAL DISCLOSURE BULLETIN", VOL 8, NO. 4, SEPTEMBRE 1965,"FIELD EFFECT TRANSISTOR CLOCKED LOGIC", C.E.RUOFF PAGES 640-641. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0022266A1 (en) * 1979-07-10 1981-01-14 Kabushiki Kaisha Toshiba Semiconductor circuit device

Also Published As

Publication number Publication date
DE2247178A1 (de) 1973-06-14
US3745370A (en) 1973-07-10
JPS528143B2 (en:Method) 1977-03-07
CA945227A (en) 1974-04-09
DE2247178B2 (de) 1975-11-13
FR2161895B1 (en:Method) 1975-03-07
JPS4865866A (en:Method) 1973-09-10
GB1340020A (en) 1973-12-05

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Legal Events

Date Code Title Description
ST Notification of lapse