FR2154855A5 - - Google Patents

Info

Publication number
FR2154855A5
FR2154855A5 FR7134796A FR7134796A FR2154855A5 FR 2154855 A5 FR2154855 A5 FR 2154855A5 FR 7134796 A FR7134796 A FR 7134796A FR 7134796 A FR7134796 A FR 7134796A FR 2154855 A5 FR2154855 A5 FR 2154855A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7134796A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telemecanique SA
Original Assignee
La Telemecanique Electrique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by La Telemecanique Electrique SA filed Critical La Telemecanique Electrique SA
Priority to FR7134796A priority Critical patent/FR2154855A5/fr
Priority to ES407096A priority patent/ES407096A1/es
Priority to BR672872A priority patent/BR7206728D0/pt
Application granted granted Critical
Publication of FR2154855A5 publication Critical patent/FR2154855A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Error Detection And Correction (AREA)
FR7134796A 1971-09-28 1971-09-28 Expired FR2154855A5 (enExample)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR7134796A FR2154855A5 (enExample) 1971-09-28 1971-09-28
ES407096A ES407096A1 (es) 1971-09-28 1972-09-28 Perfeccionamientos en circuitos destinados a establecer unajerarquia entre dos grupos de informaciones binarias.
BR672872A BR7206728D0 (pt) 1971-09-28 1972-09-28 Circuito destinado a estabelecer uma hierarquia entre dois grupos de informacoes binarias

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7134796A FR2154855A5 (enExample) 1971-09-28 1971-09-28

Publications (1)

Publication Number Publication Date
FR2154855A5 true FR2154855A5 (enExample) 1973-05-18

Family

ID=9083565

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7134796A Expired FR2154855A5 (enExample) 1971-09-28 1971-09-28

Country Status (3)

Country Link
BR (1) BR7206728D0 (enExample)
ES (1) ES407096A1 (enExample)
FR (1) FR2154855A5 (enExample)

Also Published As

Publication number Publication date
ES407096A1 (es) 1975-10-01
BR7206728D0 (pt) 1973-08-30

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Legal Events

Date Code Title Description
TP Transmission of property