ES407096A1 - Perfeccionamientos en circuitos destinados a establecer unajerarquia entre dos grupos de informaciones binarias. - Google Patents

Perfeccionamientos en circuitos destinados a establecer unajerarquia entre dos grupos de informaciones binarias.

Info

Publication number
ES407096A1
ES407096A1 ES407096A ES407096A ES407096A1 ES 407096 A1 ES407096 A1 ES 407096A1 ES 407096 A ES407096 A ES 407096A ES 407096 A ES407096 A ES 407096A ES 407096 A1 ES407096 A1 ES 407096A1
Authority
ES
Spain
Prior art keywords
bit
group
groups
rank
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES407096A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telemecanique SA
Original Assignee
La Telemecanique Electrique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by La Telemecanique Electrique SA filed Critical La Telemecanique Electrique SA
Publication of ES407096A1 publication Critical patent/ES407096A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Error Detection And Correction (AREA)
ES407096A 1971-09-28 1972-09-28 Perfeccionamientos en circuitos destinados a establecer unajerarquia entre dos grupos de informaciones binarias. Expired ES407096A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7134796A FR2154855A5 (enExample) 1971-09-28 1971-09-28

Publications (1)

Publication Number Publication Date
ES407096A1 true ES407096A1 (es) 1975-10-01

Family

ID=9083565

Family Applications (1)

Application Number Title Priority Date Filing Date
ES407096A Expired ES407096A1 (es) 1971-09-28 1972-09-28 Perfeccionamientos en circuitos destinados a establecer unajerarquia entre dos grupos de informaciones binarias.

Country Status (3)

Country Link
BR (1) BR7206728D0 (enExample)
ES (1) ES407096A1 (enExample)
FR (1) FR2154855A5 (enExample)

Also Published As

Publication number Publication date
FR2154855A5 (enExample) 1973-05-18
BR7206728D0 (pt) 1973-08-30

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