FR2134406B1 - - Google Patents

Info

Publication number
FR2134406B1
FR2134406B1 FR7214239A FR7214239A FR2134406B1 FR 2134406 B1 FR2134406 B1 FR 2134406B1 FR 7214239 A FR7214239 A FR 7214239A FR 7214239 A FR7214239 A FR 7214239A FR 2134406 B1 FR2134406 B1 FR 2134406B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7214239A
Other versions
FR2134406A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2134406A1 publication Critical patent/FR2134406A1/fr
Application granted granted Critical
Publication of FR2134406B1 publication Critical patent/FR2134406B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Communication Control (AREA)
  • Semiconductor Memories (AREA)
FR7214239A 1971-04-23 1972-04-21 Expired FR2134406B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7105512A NL7105512A (fr) 1971-04-23 1971-04-23

Publications (2)

Publication Number Publication Date
FR2134406A1 FR2134406A1 (fr) 1972-12-08
FR2134406B1 true FR2134406B1 (fr) 1976-10-29

Family

ID=19812998

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7214239A Expired FR2134406B1 (fr) 1971-04-23 1972-04-21

Country Status (6)

Country Link
US (1) US3727204A (fr)
JP (1) JPS5322819B1 (fr)
DE (1) DE2216465C3 (fr)
FR (1) FR2134406B1 (fr)
GB (1) GB1387882A (fr)
NL (1) NL7105512A (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123527A (fr) * 1973-03-30 1974-11-26
JPS5340445B2 (fr) * 1973-08-15 1978-10-27
US4204250A (en) * 1977-08-04 1980-05-20 Honeywell Information Systems Inc. Range count and main memory address accounting system
FR2450008A1 (fr) * 1979-02-21 1980-09-19 Portejoie Jean Francois Circuit de synchronisation de signaux numeriques plesiochrones par justification
US4296477A (en) * 1979-11-19 1981-10-20 Control Data Corporation Register device for transmission of data having two data ranks one of which receives data only when the other is full
JPS57164331A (en) * 1981-04-02 1982-10-08 Nec Corp Buffer controller
US4837740A (en) * 1985-01-04 1989-06-06 Sutherland Ivan F Asynchronous first-in-first-out register structure
US4679213A (en) * 1985-01-08 1987-07-07 Sutherland Ivan E Asynchronous queue system
US4907187A (en) * 1985-05-17 1990-03-06 Sanyo Electric Co., Ltd. Processing system using cascaded latches in a transmission path for both feedback and forward transfer of data
AR242675A1 (es) * 1985-10-11 1993-04-30 Ibm Una disposiciones de almacenamiento intermedio de voz
US5550780A (en) * 1994-12-19 1996-08-27 Cirrus Logic, Inc. Two cycle asynchronous FIFO queue
JP4302515B2 (ja) * 2001-07-16 2009-07-29 デピュイ・プロダクツ・インコーポレイテッド 単体型外科装置および方法
US7971038B2 (en) * 2005-09-05 2011-06-28 Nxp B.V. Asynchronous ripple pipeline

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997704A (en) * 1958-02-24 1961-08-22 Epsco Inc Signal conversion apparatus
IT614744A (fr) * 1958-08-29 1900-01-01
US3051929A (en) * 1959-03-13 1962-08-28 Bell Telephone Labor Inc Digital data converter
US3214573A (en) * 1961-08-10 1965-10-26 Gen Time Corp Digital storage and readout device

Also Published As

Publication number Publication date
NL7105512A (fr) 1972-10-25
GB1387882A (en) 1975-03-19
US3727204A (en) 1973-04-10
DE2216465C3 (de) 1979-05-10
DE2216465A1 (de) 1972-10-26
JPS5322819B1 (fr) 1978-07-11
JPS4741252A (fr) 1972-12-13
DE2216465B2 (de) 1978-09-07
FR2134406A1 (fr) 1972-12-08

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Legal Events

Date Code Title Description
ST Notification of lapse