FR1599127A - - Google Patents

Info

Publication number
FR1599127A
FR1599127A FR176313A FR1599127DA FR1599127A FR 1599127 A FR1599127 A FR 1599127A FR 176313 A FR176313 A FR 176313A FR 1599127D A FR1599127D A FR 1599127DA FR 1599127 A FR1599127 A FR 1599127A
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR176313A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Application granted granted Critical
Publication of FR1599127A publication Critical patent/FR1599127A/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
FR176313A 1968-12-03 1968-12-03 Expired FR1599127A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR176313 1968-12-03

Publications (1)

Publication Number Publication Date
FR1599127A true FR1599127A (fr) 1970-07-15

Family

ID=8657744

Family Applications (1)

Application Number Title Priority Date Filing Date
FR176313A Expired FR1599127A (fr) 1968-12-03 1968-12-03

Country Status (4)

Country Link
US (1) US3803426A (fr)
DE (1) DE1960525B2 (fr)
FR (1) FR1599127A (fr)
GB (1) GB1257116A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5588430A (en) * 1978-12-22 1980-07-04 Ibm Unsaturated nor logic circuit
US4831283A (en) * 1988-05-16 1989-05-16 Bnr Inc. Terminator current driver with short-circuit protection

Also Published As

Publication number Publication date
US3803426A (en) 1974-04-09
DE1960525B2 (de) 1971-11-04
DE1960525A1 (de) 1970-06-11
GB1257116A (fr) 1971-12-15

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Legal Events

Date Code Title Description
ST Notification of lapse