FR1485079A - Système de transmission de donnée synchronisé par des bits départ-arrêt - Google Patents
Système de transmission de donnée synchronisé par des bits départ-arrêtInfo
- Publication number
- FR1485079A FR1485079A FR7913A FR06007913A FR1485079A FR 1485079 A FR1485079 A FR 1485079A FR 7913 A FR7913 A FR 7913A FR 06007913 A FR06007913 A FR 06007913A FR 1485079 A FR1485079 A FR 1485079A
- Authority
- FR
- France
- Prior art keywords
- data transmission
- transmission system
- stop bits
- system synchronized
- synchronized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0262—Arrangements for detecting the data rate of an incoming signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Selective Calling Equipment (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US469491A US3388216A (en) | 1965-07-06 | 1965-07-06 | Start-stop synchronous data transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1485079A true FR1485079A (fr) | 1967-06-16 |
Family
ID=23863997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7913A Expired FR1485079A (fr) | 1965-07-06 | 1966-06-22 | Système de transmission de donnée synchronisé par des bits départ-arrêt |
Country Status (4)
Country | Link |
---|---|
US (1) | US3388216A (fr) |
DE (1) | DE1462689A1 (fr) |
FR (1) | FR1485079A (fr) |
GB (1) | GB1121373A (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH457541A (de) * | 1966-06-08 | 1968-06-15 | Hasler Ag | Vorrichtung zur Erzeugung synchronisierter Taktimpulse in einem Empfänger rhythmischer Signale |
US3509471A (en) * | 1966-11-16 | 1970-04-28 | Communications Satellite Corp | Digital phase lock loop for bit timing recovery |
DE1512538B2 (de) * | 1966-12-22 | 1970-09-10 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Verfahren und Anordnung zur empfangsseitigen Bestimmung der Sendegeschwindigkeit einer Folge von Fernschreibzeichen im Start-Stop-Betrieb und Anpassung des Empfangsgerätes an den ermittelten Sendetakt |
DE3390204C2 (de) * | 1983-02-28 | 1989-09-14 | Mitsubishi Electric Corp | Verfahren zum ]bertragen von PCM-kodierten Datensignalen |
DE3504983C2 (de) * | 1984-02-22 | 1997-12-11 | Philips Electronics Nv | Datenübertragungsanordnung |
CH675183A5 (fr) * | 1987-11-23 | 1990-08-31 | Koechler Erika Fa | |
US5128971A (en) * | 1991-01-14 | 1992-07-07 | Motorola, Inc. | Frequency synchronization apparatus |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3112363A (en) * | 1960-02-22 | 1963-11-26 | Philips Corp | Device to shift a block signal to a given mean phase and to hold it therein with respect to the pulse instants of an incoming pulse sequence |
US3209265A (en) * | 1963-07-09 | 1965-09-28 | Bell Telephone Labor Inc | Data receiver synchronizer for advancing or retarding phase of output after sampling over period of time |
-
1965
- 1965-07-06 US US469491A patent/US3388216A/en not_active Expired - Lifetime
-
1966
- 1966-06-22 FR FR7913A patent/FR1485079A/fr not_active Expired
- 1966-06-23 GB GB28033/66A patent/GB1121373A/en not_active Expired
- 1966-07-02 DE DE19661462689 patent/DE1462689A1/de active Pending
Also Published As
Publication number | Publication date |
---|---|
GB1121373A (en) | 1968-07-24 |
DE1462689A1 (de) | 1968-11-21 |
US3388216A (en) | 1968-06-11 |
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