FR1174193A - Additionneur parallèle à report rapide - Google Patents

Additionneur parallèle à report rapide

Info

Publication number
FR1174193A
FR1174193A FR1174193DA FR1174193A FR 1174193 A FR1174193 A FR 1174193A FR 1174193D A FR1174193D A FR 1174193DA FR 1174193 A FR1174193 A FR 1174193A
Authority
FR
France
Prior art keywords
parallel adder
fast carry
carry parallel
fast
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Application granted granted Critical
Publication of FR1174193A publication Critical patent/FR1174193A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
FR1174193D 1956-04-12 1957-04-12 Additionneur parallèle à report rapide Expired FR1174193A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US361417XA 1956-04-12 1956-04-12

Publications (1)

Publication Number Publication Date
FR1174193A true FR1174193A (fr) 1959-03-06

Family

ID=21886884

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1174193D Expired FR1174193A (fr) 1956-04-12 1957-04-12 Additionneur parallèle à report rapide

Country Status (5)

Country Link
BE (1) BE556428A (enrdf_load_stackoverflow)
CH (1) CH361417A (enrdf_load_stackoverflow)
FR (1) FR1174193A (enrdf_load_stackoverflow)
GB (1) GB833781A (enrdf_load_stackoverflow)
NL (1) NL216061A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3325634A (en) * 1964-02-03 1967-06-13 Hughes Aircraft Co Dynamic high speed parallel adder using tunnel diode circuits

Also Published As

Publication number Publication date
CH361417A (de) 1962-04-15
GB833781A (en) 1960-04-27
NL216061A (enrdf_load_stackoverflow)
BE556428A (enrdf_load_stackoverflow)

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