FR111566A - - Google Patents
Info
- Publication number
- FR111566A FR111566A FR111566DA FR111566A FR 111566 A FR111566 A FR 111566A FR 111566D A FR111566D A FR 111566DA FR 111566 A FR111566 A FR 111566A
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7433602A FR2287067A1 (fr) | 1974-10-04 | 1974-10-04 | Dispositif de tamponnage d'informations entre un processeur et sa memoire principale |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR111566A true FR111566A (de) |
Family
ID=9143790
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR111566D Active FR111566A (de) | 1974-10-04 | ||
| FR7433602A Granted FR2287067A1 (fr) | 1974-10-04 | 1974-10-04 | Dispositif de tamponnage d'informations entre un processeur et sa memoire principale |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7433602A Granted FR2287067A1 (fr) | 1974-10-04 | 1974-10-04 | Dispositif de tamponnage d'informations entre un processeur et sa memoire principale |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5191634A (de) |
| FR (2) | FR2287067A1 (de) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2412139B1 (fr) * | 1977-12-16 | 1986-05-09 | Honeywell Inf Systems | Circuits de directives d'antememoire |
| US4309754A (en) * | 1979-07-30 | 1982-01-05 | International Business Machines Corp. | Data interface mechanism for interfacing bit-parallel data buses of different bit width |
| US4467414A (en) * | 1980-08-22 | 1984-08-21 | Nippon Electric Co., Ltd. | Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories |
| JPH0644245B2 (ja) * | 1983-12-29 | 1994-06-08 | 富士通株式会社 | ストアバッファ装置 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2261586C3 (de) * | 1972-12-15 | 1979-08-09 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Speichereinrichtung |
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0
- FR FR111566D patent/FR111566A/fr active Active
-
1974
- 1974-10-04 FR FR7433602A patent/FR2287067A1/fr active Granted
-
1975
- 1975-10-03 JP JP50119033A patent/JPS5191634A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2287067A1 (fr) | 1976-04-30 |
| FR2287067B1 (de) | 1977-11-04 |
| JPS5191634A (de) | 1976-08-11 |