FI952055A - Näytteitysmenetelmä ja -laite, etenkin johdottomia televiestintälaitteita varten - Google Patents
Näytteitysmenetelmä ja -laite, etenkin johdottomia televiestintälaitteita varten Download PDFInfo
- Publication number
- FI952055A FI952055A FI952055A FI952055A FI952055A FI 952055 A FI952055 A FI 952055A FI 952055 A FI952055 A FI 952055A FI 952055 A FI952055 A FI 952055A FI 952055 A FI952055 A FI 952055A
- Authority
- FI
- Finland
- Prior art keywords
- wireless telecommunications
- sampling method
- telecommunications equipment
- equipment
- sampling
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4236775A DE4236775C2 (de) | 1992-10-30 | 1992-10-30 | Abtastverfahren und -einrichtung, insbesondere für Schnurlos-Telekommunikationsgeräte |
PCT/DE1993/000973 WO1994010777A1 (de) | 1992-10-30 | 1993-10-12 | Abtastverfahren und -einrichtung, insbesondere für schnurlos-telekommunikationsgeräte |
Publications (2)
Publication Number | Publication Date |
---|---|
FI952055A true FI952055A (fi) | 1995-04-28 |
FI952055A0 FI952055A0 (fi) | 1995-04-28 |
Family
ID=6471793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI952055A FI952055A0 (fi) | 1992-10-30 | 1995-04-28 | Näytteitysmenetelmä ja -laite, etenkin johdottomia televiestintälaitteita varten |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0667073B1 (fi) |
AU (1) | AU5147893A (fi) |
DE (2) | DE4236775C2 (fi) |
ES (1) | ES2102063T3 (fi) |
FI (1) | FI952055A0 (fi) |
HK (1) | HK1001079A1 (fi) |
WO (1) | WO1994010777A1 (fi) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19638412C2 (de) * | 1996-09-19 | 1998-09-17 | Siemens Ag | Verfahren zum Bestimmen einer Abtastphase |
DE19911715B4 (de) * | 1999-03-16 | 2005-07-21 | Siemens Ag | Verfahren und Vorrichtung zur Rahmensynchronisation in einem Zeitmultiplexsystem |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2219016C3 (de) * | 1972-04-19 | 1978-11-30 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Verfahren zur empfangsseitigen Phasensynchronisation auf die Phasenlage des Bittaktes eines empfangenen Datenblocks |
DE3611959A1 (de) * | 1986-04-09 | 1987-10-22 | Siemens Ag | Synchronisierverfahren |
EP0268694B1 (de) * | 1986-11-22 | 1991-02-20 | ANT Nachrichtentechnik GmbH | Verfahren zur Synchronisation auf im Zeitmultiplexbetrieb ausgesendete Signale und zur Taktgewinnung hieraus |
DE3806428C2 (de) * | 1988-02-29 | 1994-07-28 | Siemens Ag | Verfahren und Schaltungsanordnung zum Ermitteln einer in einem Serienbitstrom enthaltenen Bitkombination |
DE3806429C2 (de) * | 1988-02-29 | 1994-09-22 | Siemens Ag | Verfahren und Schaltungsanordnung zum Ermitteln einer in einem Serienbitstrom enthaltenen Bitkombination |
US5103466A (en) * | 1990-03-26 | 1992-04-07 | Intel Corporation | CMOS digital clock and data recovery circuit |
-
1992
- 1992-10-30 DE DE4236775A patent/DE4236775C2/de not_active Expired - Lifetime
-
1993
- 1993-10-12 DE DE59306414T patent/DE59306414D1/de not_active Expired - Lifetime
- 1993-10-12 WO PCT/DE1993/000973 patent/WO1994010777A1/de active IP Right Grant
- 1993-10-12 ES ES93922490T patent/ES2102063T3/es not_active Expired - Lifetime
- 1993-10-12 EP EP93922490A patent/EP0667073B1/de not_active Expired - Lifetime
- 1993-10-12 AU AU51478/93A patent/AU5147893A/en not_active Abandoned
-
1995
- 1995-04-28 FI FI952055A patent/FI952055A0/fi not_active Application Discontinuation
-
1998
- 1998-01-09 HK HK98100175A patent/HK1001079A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0667073B1 (de) | 1997-05-07 |
EP0667073A1 (de) | 1995-08-16 |
DE4236775C2 (de) | 1994-08-18 |
FI952055A0 (fi) | 1995-04-28 |
WO1994010777A1 (de) | 1994-05-11 |
DE59306414D1 (de) | 1997-06-12 |
AU5147893A (en) | 1994-05-24 |
HK1001079A1 (en) | 1998-05-22 |
ES2102063T3 (es) | 1997-07-16 |
DE4236775A1 (de) | 1994-05-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD | Application lapsed |