FI934231A0 - Menetelmä vaihelukitun silmukan ohjaamiseksi sekä vaihelukittu silmukka - Google Patents
Menetelmä vaihelukitun silmukan ohjaamiseksi sekä vaihelukittu silmukkaInfo
- Publication number
- FI934231A0 FI934231A0 FI934231A FI934231A FI934231A0 FI 934231 A0 FI934231 A0 FI 934231A0 FI 934231 A FI934231 A FI 934231A FI 934231 A FI934231 A FI 934231A FI 934231 A0 FI934231 A0 FI 934231A0
- Authority
- FI
- Finland
- Prior art keywords
- phase
- locked loop
- controlling
- locked
- loop
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
- H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
- H03L7/145—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop the switched reference signal being derived from the controlled oscillator output signal
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI934231A FI97003C (fi) | 1993-09-27 | 1993-09-27 | Menetelmä vaihelukitun silmukan ohjaamiseksi sekä vaihelukittu silmukka |
PCT/FI1994/000432 WO1995009485A1 (en) | 1993-09-27 | 1994-09-26 | Method for controlling a phase-locked loop, and a phase-locked loop |
EP94927679A EP0721698B1 (en) | 1993-09-27 | 1994-09-26 | Method for controlling a phase-locked loop, and a phase-locked loop |
AU77003/94A AU7700394A (en) | 1993-09-27 | 1994-09-26 | Method for controlling a phase-locked loop, and a phase-locked loop |
DE69422990T DE69422990T2 (de) | 1993-09-27 | 1994-09-26 | Verfahren zur steuerung eines phasenregelkreises und phasenregelkreis |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI934231 | 1993-09-27 | ||
FI934231A FI97003C (fi) | 1993-09-27 | 1993-09-27 | Menetelmä vaihelukitun silmukan ohjaamiseksi sekä vaihelukittu silmukka |
Publications (4)
Publication Number | Publication Date |
---|---|
FI934231A0 true FI934231A0 (fi) | 1993-09-27 |
FI934231A FI934231A (fi) | 1995-03-28 |
FI97003B FI97003B (fi) | 1996-06-14 |
FI97003C FI97003C (fi) | 1996-09-25 |
Family
ID=8538669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI934231A FI97003C (fi) | 1993-09-27 | 1993-09-27 | Menetelmä vaihelukitun silmukan ohjaamiseksi sekä vaihelukittu silmukka |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0721698B1 (fi) |
AU (1) | AU7700394A (fi) |
DE (1) | DE69422990T2 (fi) |
FI (1) | FI97003C (fi) |
WO (1) | WO1995009485A1 (fi) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AR031519A1 (es) * | 1999-05-06 | 2003-09-24 | Navcom Tech Inc | Un transmisor de senales de radio, un receptor de senales, un dispositivo de comunicaciones y un metodo |
US7010076B1 (en) * | 1999-10-29 | 2006-03-07 | Adc Telecommunications, Inc. | Systems and methods for holdover circuits in phase locked loops |
US6313708B1 (en) * | 2000-07-26 | 2001-11-06 | Marconi Communications, Inc. | Analog phase locked loop holdover |
US10574242B2 (en) * | 2017-10-12 | 2020-02-25 | Synaptics Incorporated | Phase locked loop sampler and restorer |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT986172B (it) * | 1973-06-18 | 1975-01-20 | Fatme Spa | Dispositivo di sincronizzazione automatica per un oscillatore in particolare per impianti di tele comunicazione |
US4531102A (en) * | 1983-02-28 | 1985-07-23 | Gk Technologies, Incorporated | Digital phase lock loop system |
IT1223524B (it) * | 1987-12-18 | 1990-09-19 | Honeywell Bull Spa | Circuito ad aggancio di fase autotarante |
-
1993
- 1993-09-27 FI FI934231A patent/FI97003C/fi active IP Right Grant
-
1994
- 1994-09-26 EP EP94927679A patent/EP0721698B1/en not_active Expired - Lifetime
- 1994-09-26 AU AU77003/94A patent/AU7700394A/en not_active Abandoned
- 1994-09-26 WO PCT/FI1994/000432 patent/WO1995009485A1/en active IP Right Grant
- 1994-09-26 DE DE69422990T patent/DE69422990T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FI97003B (fi) | 1996-06-14 |
WO1995009485A1 (en) | 1995-04-06 |
FI97003C (fi) | 1996-09-25 |
DE69422990D1 (de) | 2000-03-16 |
DE69422990T2 (de) | 2000-06-29 |
AU7700394A (en) | 1995-04-18 |
EP0721698A1 (en) | 1996-07-17 |
EP0721698B1 (en) | 2000-02-09 |
FI934231A (fi) | 1995-03-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG | Patent granted |
Owner name: NOKIA TELECOMMUNICATIONS OY |
|
BB | Publication of examined application |