FI843755L - PROCESSING FOR FELIDENTIFICATION WITH DOUBLE COPPER, SAERSKILT PROCESSORER WITH ETF TELEFONFOERMEDLINGSSYSTEM. - Google Patents

PROCESSING FOR FELIDENTIFICATION WITH DOUBLE COPPER, SAERSKILT PROCESSORER WITH ETF TELEFONFOERMEDLINGSSYSTEM.

Info

Publication number
FI843755L
FI843755L FI843755A FI843755A FI843755L FI 843755 L FI843755 L FI 843755L FI 843755 A FI843755 A FI 843755A FI 843755 A FI843755 A FI 843755A FI 843755 L FI843755 L FI 843755L
Authority
FI
Finland
Prior art keywords
telefonfoermedlingssystem
processorer
felidentification
saerskilt
etf
Prior art date
Application number
FI843755A
Other languages
Finnish (fi)
Other versions
FI843755A0 (en
Inventor
Rudolf Bitzinger
Walter Engl
Siegfried Humml
Klaus Schreier
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI843755A0 publication Critical patent/FI843755A0/en
Publication of FI843755L publication Critical patent/FI843755L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Multi Processors (AREA)
FI843755A 1983-09-26 1984-09-25 PROCESSING FOR FELIDENTIFICATION WITH DOUBLE COPPER, SAERSKILT PROCESSORER WITH ETF TELEFONFOERMEDLINGSSYSTEM. FI843755L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833334765 DE3334765A1 (en) 1983-09-26 1983-09-26 TEST DEVICE FOR DETECTING ERRORS IN DOUBLE CIRCUITS, IN PARTICULAR PROCESSORS OF A TELEPHONE SWITCHING SYSTEM

Publications (2)

Publication Number Publication Date
FI843755A0 FI843755A0 (en) 1984-09-25
FI843755L true FI843755L (en) 1985-03-27

Family

ID=6210074

Family Applications (1)

Application Number Title Priority Date Filing Date
FI843755A FI843755L (en) 1983-09-26 1984-09-25 PROCESSING FOR FELIDENTIFICATION WITH DOUBLE COPPER, SAERSKILT PROCESSORER WITH ETF TELEFONFOERMEDLINGSSYSTEM.

Country Status (5)

Country Link
EP (1) EP0140155A3 (en)
JP (1) JPS6093558A (en)
DE (1) DE3334765A1 (en)
FI (1) FI843755L (en)
ZA (1) ZA847564B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334765A1 (en) * 1983-09-26 1985-04-11 Siemens AG, 1000 Berlin und 8000 München TEST DEVICE FOR DETECTING ERRORS IN DOUBLE CIRCUITS, IN PARTICULAR PROCESSORS OF A TELEPHONE SWITCHING SYSTEM
DE3629399A1 (en) * 1986-08-29 1988-03-03 Siemens Ag Method for operating the central memory of a multiprocessor-type common control unit of a switching system
US4816990A (en) * 1986-11-05 1989-03-28 Stratus Computer, Inc. Method and apparatus for fault-tolerant computer system having expandable processor section
SE463900B (en) * 1989-06-16 1991-02-04 Ericsson Telefon Ab L M PROCEDURE AND DEVICE AT A MULTIPLE PLAN UNIT IN A DIGITAL TIMER SELECTOR TO DETECT AND LOCATE ERRORS
US5280487A (en) * 1989-06-16 1994-01-18 Telefonaktiebolaget L M Ericsson Method and arrangement for detecting and localizing errors or faults in a multi-plane unit incorporated in a digital time switch
DE10131920A1 (en) * 2001-07-02 2003-01-23 Tenovis Gmbh & Co Kg Communication installation with distributed control, has each equipment module provided with emergency operation-control unit for switching to emergency operation mode

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982111A (en) * 1975-08-04 1976-09-21 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
US4020459A (en) * 1975-10-28 1977-04-26 Bell Telephone Laboratories, Incorporated Parity generation and bus matching arrangement for synchronized duplicated data processing units
IT1209187B (en) * 1980-02-11 1989-07-16 Sits Soc It Telecom Siemens CONTROL DEVICE FOR THE CORRECT OPERATION OF A COUPLE OF PROCESSORS OPERATING ONE AS THE HOT RESERVE OF THE OTHER.
JPS56124956A (en) * 1980-03-06 1981-09-30 Nec Corp Double information processing equipment
IT8024701A0 (en) * 1980-09-17 1980-09-17 Italtel Spa CIRCUIT ARRANGEMENT SUITABLE FOR DETECTING THE PRESENCE OF MALFUNCTIONS IN A DATA PROCESSING SYSTEM USING A COMMERCIAL TYPE MICROPROCESSOR.
DE3334765A1 (en) * 1983-09-26 1985-04-11 Siemens AG, 1000 Berlin und 8000 München TEST DEVICE FOR DETECTING ERRORS IN DOUBLE CIRCUITS, IN PARTICULAR PROCESSORS OF A TELEPHONE SWITCHING SYSTEM

Also Published As

Publication number Publication date
JPS6093558A (en) 1985-05-25
FI843755A0 (en) 1984-09-25
EP0140155A3 (en) 1988-02-10
ZA847564B (en) 1985-05-29
DE3334765A1 (en) 1985-04-11
EP0140155A2 (en) 1985-05-08

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Owner name: SIEMENS AKTIENGESELLSCHAFT