FI770899A7 - - Google Patents

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Info

Publication number
FI770899A7
FI770899A7 FI770899A FI770899A FI770899A7 FI 770899 A7 FI770899 A7 FI 770899A7 FI 770899 A FI770899 A FI 770899A FI 770899 A FI770899 A FI 770899A FI 770899 A7 FI770899 A7 FI 770899A7
Authority
FI
Finland
Application number
FI770899A
Other languages
Finnish (fi)
Inventor
Rene Deglin
Gilbert Reymond
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Publication of FI770899A7 publication Critical patent/FI770899A7/fi

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Programmable Controllers (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Exchange Systems With Centralized Control (AREA)
FI770899A 1976-03-31 1977-03-22 FI770899A7 (cs)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7609391A FR2356202A1 (fr) 1976-03-31 1976-03-31 Logique sequentielle programmable

Publications (1)

Publication Number Publication Date
FI770899A7 true FI770899A7 (cs) 1977-10-01

Family

ID=9171239

Family Applications (1)

Application Number Title Priority Date Filing Date
FI770899A FI770899A7 (cs) 1976-03-31 1977-03-22

Country Status (11)

Country Link
US (1) US4237545A (cs)
JP (1) JPS52120642A (cs)
BE (1) BE852499A (cs)
DE (1) DE2713068A1 (cs)
ES (1) ES457282A1 (cs)
FI (1) FI770899A7 (cs)
FR (1) FR2356202A1 (cs)
GB (1) GB1580328A (cs)
IT (1) IT1076275B (cs)
NL (1) NL7703345A (cs)
SE (1) SE7703523L (cs)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5778439A (en) * 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5701441A (en) * 1995-08-18 1997-12-23 Xilinx, Inc. Computer-implemented method of optimizing a design in a time multiplexed programmable logic device
US5761483A (en) * 1995-08-18 1998-06-02 Xilinx, Inc. Optimizing and operating a time multiplexed programmable logic device
US6047115A (en) * 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US9927323B2 (en) * 2012-10-26 2018-03-27 Acellent Technologies, Inc. System and method for monitoring the structural health of coupled bearings

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210733A (en) * 1958-08-18 1965-10-05 Sylvania Electric Prod Data processing system
US3340513A (en) * 1964-08-28 1967-09-05 Gen Precision Inc Instruction and operand processing
US3430202A (en) * 1964-10-07 1969-02-25 Bell Telephone Labor Inc Data processor utilizing combined order instructions
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding

Also Published As

Publication number Publication date
FR2356202A1 (fr) 1978-01-20
NL7703345A (nl) 1977-10-04
US4237545A (en) 1980-12-02
ES457282A1 (es) 1978-02-01
SE7703523L (sv) 1977-10-01
IT1076275B (it) 1985-04-27
JPS52120642A (en) 1977-10-11
BE852499A (fr) 1977-09-16
DE2713068A1 (de) 1977-10-13
GB1580328A (en) 1980-12-03

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Legal Events

Date Code Title Description
FD Application lapsed

Owner name: COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-