FI73853B - KOMPATIBELT, TRANSKODBART OCH HIERARKISKT DIGITALT TELEVISIONSSYSTEM. - Google Patents

Description

The present invention relates to a digital television-5 system that conforms to most global television standards.......................................... The invention relates to arrangements for easy transmission coding between video signals sampled at different frequencies.

Various features of 10 global standards for compatible digital television have already been considered. In various contexts, it has been suggested that there should be an equal number of samples over the total horizontal line duration in both the 525-line 60 Hz (NTSC) and 625-line 50 Hz (PAL / SECAM) systems, or possibly the same number of samples during the active portion of each line. Among the factors relevant to such a global standard are the sampling rate suitable for systems with limited bandwidth, which still has a satisfactory accuracy of 20, and the question of whether the standard should be a combined luminescence-color system as opposed to component systems such as RGB or YIQ.

It is also desirable to use a digital television standard that is hierarchical. A hierarchical system is one in which different levels or levels of detail or services can be simply transmitted, e.g., by filtering and removing samples. Thus, a digital system could allow signals to be generated at a very high sampling rate, providing a resolution suitable for cinema-type use. Such a resolution could be as much as 2,000 lines in a raster vertically and 2,000 television lines in a horizontal direction. For editing purposes, television producers might wish to use a higher resolution than the standard resolution of a television, but might wish to use equipment that is not as expensive as that capable of operating at 2,000 lines of __ - ... TT- __ 2 73853 terin. required data rates. Thus, a television producer could use hardware capable of operating the second level of the hierarchy, which is 1000 line resolution. If the producer had access to a recording made at the resolution of the original 2000 lines, the removal and filtering of alternating samples from each line would reduce the resolution to the level of 1000 lines. The next level in the hierarchy could be a 500-line resolution that could be used at a television broadcast station 10 to generate analog video information for home transmission. The tape edited by the television producer could be used at the transmitting station in equipment capable of 500 lines resolution by removing every other sample. Alternatively, a television station could use a strip of 2000 15 lines resolution, always removing three samples from each of the four. The next step in the hierarchy could be applicable to electronic news chambers using a resolution of 250 lines, and the next lower level of resolution could be used for control functions.

It is generally expected that in the United States and other countries using NTSC standards, hardware will generally be available for processing television signals in their combined form. It is highly preferred that the sampling frequency of such devices is an integer multiple of the frequency of the color subcarrier, such as 3 or 4 times this frequency (3 x SC, 4 x SC). It seems very likely that when the global standard for digital television is finally adopted, it will not be based on a sampling frequency locked to a color subcarrier. However, it is highly desirable that the subcompressed, sampled composite video be easily transcodable to have the features of this standard when the standard is adopted. In all likelihood, this transcoding requires interpolation of the sample values to a global standard based on the values of the nearest adjacent 3,73853 samples in the NTSC composite video. Of course, the samples would be identical to each other and no interpolation would be necessary if the clock frequencies were identical to each other. Accurate interpolation is complex and requires multiplication and addition operations for each interpolated sample. In particular, multipliers tend to be slow in operation, and to be able to achieve operation at high frequencies of video data, they can be expected to be expensive. 10 It would be highly desirable to have a global television standard for digital video that is compatible with both the 625/50 and 525/60 standards in terms of sampling frequency. The system should be hierarchical and should also be easily transmission-encodable from the composite NTSC video sampled multiple times of the subcarrier frequency to the second without the use of multipliers.

The original standard horizontal line frequency for black and white NTSC TV was 15,750 20 hertz. With the introduction of color systems, the line frequency was changed to be based on the 4.5 MHz audio subcarrier frequency. The exact frequency of the horizontal lines is 1/286 x 4.5 MHz, which has been standardized by CCIR to 15,734,264 + 0.0003% hertz. Subsequently, the FCC has defined the frequency of 25 color subcarriers in megahertz as a quotient of 315/88, and the line frequency is 2/455 times this subcarrier frequency, resulting in approximately 15,734,266. When using the 625/50 standard, the horizontal line frequency is 15,625 Hertz.

It is known that a common clock frequency of exactly 13.5 MHz produces exactly 864 samples per horizontal line in a 625/50 system, and that it implements exactly 858 samples per line in a 525/60 system. Thus, the 13.5 MHz sampling frequency (and other sampling frequencies that differ from this by 2.25 MHz by 35 multiples) provides an integer number of samples per line in each system.

The duration of the horizontal line in the 625/50 system is 64.00 μs and in the 525/60 system the duration is approximately 63.56 μs. The CCIR standards for the 625/50 system define an active line duration of approximately 52 microseconds with a shutdown duration of 12 microseconds. The duration of the shutdown is 10.9 + 0.2 ^ us according to the current NTSC color standards, but proposals have been made to amend this standard. Thus, the duration of the shutdown is not precisely defined in the NTSC standard. Assuming that the active line duration in the 525/60 standard is also 52, a sample rate of 702 samples is obtained at 13.5 MHz for the active portion of each line. However, the number of samples present during the quench duration varies from 162 using the 625/50 system to 156 using the 525/60 15 system.

The present invention relates to a sampling system for a television according to claim 1. The invention also relates to receivers according to claims 14 and 15 for digital television signals 20. The invention further relates to a digital color television transmission system according to claim 20.

The transmission coding scheme converts signals sampled at a particular first frequency into second signals that are clocked at the second frequency. These said first and second frequencies are selected such that their quotient is a ratio of integers. This results in renewable blocks of samples with an integer number of input samples and also samples of the new 30 outputs. The transmission encoder uses delay portions to form successive delayed samples from the input signal. The subtraction means generates the difference signals and represents the amplitude difference between the successive delayed samples. The multiplier-35 couplers connected to the difference calculators multiply the difference signals by a continuously variable multiplier to form weighted difference signals. The continuously variable multiplier is based on the effective position of the new sample to be generated 5 73853 in each sample transfer coding block. The weighted difference signals are summed in an adder to form the value of the new sample. In a preferred embodiment of the invention, the ratio of the first and second frequencies is selected to be the ratio of a certain integer M to a second power (2), resulting in sample blocks with 2r new samples, with the result that the rotating means may preferably be 10 la transfer and aggregation types.

Explanation of the drawings.

Figure 1 is a block diagram of a television system including a digital portion in accordance with an aspect of the present invention.

Figure 2 illustrates timing signals useful in understanding certain features of the arrangement of Figure 1.

Fig. 3 is a timing diagram useful in understanding different sampling times when transcoding 20 composite NTSC color television signals into signals in accordance with the standards of the arrangement of Fig. 1.

Figure 4 illustrates a general waveform that helps to understand the errors that occur during transmission coding by interpolation at new sampling points for the values of the signal from which the samples were initially taken.

Figure 5 is a block diagram of an embodiment of the invention that includes transmission coding.

FIG. 6 is a timing diagram useful in understanding relative sampling times when transcoding PAL signals into signals in accordance with the standards of the non-Figure 1 arrangement.

Fig. 7 is a printout listing the weighting factors of the interpolation 35 for PAL transmission coding.

Figures 8, 9 and 10 are general waveforms that help to understand the errors that occur when transmission is encoded by interpolation in the general case.

Fig. 11 is a block diagram illustrating a general interpolator similar to the interpolator of Fig. 5.

Figure 12 is a more detailed block diagram of a general interpolator suitable for enhanced interpolation of signals in PAL to 13.5 MHz transmission coding.

Fig. 13 is a block diagram of a digital arrangement for dividing the input signal x by a number in format 2 and multiplying the result by a continuously variable factor p.

Figure 14 is a block diagram of a general interpolator in accordance with one aspect of the present invention.

Figure 15 lists the interpretation from form n to form n 'for a particular transmission coding.

Fig. 16 is a block diagram of one form n to an alternative embodiment of the n 'form interpreter.

Figure 1 illustrates an arrangement according to the invention. In Figure 1, analog red (R), green (G) and blue (B) signals are obtained together with a horizontal synchronization signal (H) from a specific source (not shown), such as a television camera. The H signal is applied to the activation input of the counter 150, while the R, G and B signals in their various conductors are applied to a suitable anti-alias prefilter 10, where the bandwidth is limited to prevent the occurrence of equivalences in the output signal. The bandwidth limited R, G and B signals are fed to an analog to digital converter (ADC) 12, where the various R, G and B signals are sampled and quantized at 13.5 MHz under the control of the clock signal input from the clock generator 14. The ADC 12 may generate R, G, and B signals at its output terminals in the form of multiple parallel channels for each signal or as a single serial channel for each signal. In the illustrated embodiment, 7 73853 8 parallel lines are used for each signal.

The signals are fed from the AD puller 12 to a port 16 which can be activated by a flip-flop 18 to allow samples 5 to pass therethrough or which can prevent samples from accessing the digital signal further processing illustrated in block 20. Digital signal processing 20 does not form part of this invention and is certain activity that is advantageous to perform in digital form. In the example case, digital signal processing may include recording, tape editing, color adjustment or mixing, or include other special functions. Digital signal processing could also simply be a transmission channel along which digital signals are transmitted to a remote location. After signal processing, the signals no longer need to be in digital form and are consequently transferred to a digital-to-analog converter (DAC) 22, where pseudo-analog samples are generated. The pseudo-analog signals thus generated are input to a smoothing filter 24 for filtering or smoothing to form suitable analog video information.

According to one aspect of the invention, port 16 is activated to define an operating line and port 25 is adjusted to allow exactly 704 samples to pass through the digital signal processor 20 during each active line. The necessary timing adjustment is provided by the flip-flop (FF) 18, counter 150, and counter 704. The H-sync signals 204 that determine the beginning of each horizontal line 30 are applied to the activation input of counter 150, and 13.5 MHz clock signals from generator 14 are applied to the second input of counter 14. counts 150 clock or sampling pulses, and at the end of this time provides an output pulse applied to the reset input-35 of the counter 150, the activation input of the counter 704, and the activation input terminal of the flip-flop: 18 so that the Q output from the flip-flop goes from Counter 704 begins counting synchronously with the samples passing through port 16, and when exactly 704 samples are counted, counter 704 provides an output signal that resets the counter 5444 and which is also applied to the reset input of flip-flop 18 so that the Q output resetting to zero, thus opening port 16 and preventing subsequent samples from passing, thus determining the end of the active time slot.

The operation of the timing arrangement of Figure 1 and the differences between the operation of 525/60 10 and 625/60 are more clearly seen in Figure 2. Figure 2a illustrates clock samples 202 which are not shown to scale. Figure 2b illustrates horizontal synchronization pulses 204 occurring at a nominal frequency of 15,734,266. From time 15 to TO, which corresponds to the beginning of the horizontal line, the counter 150 counts down to time t150 as illustrated in Figure 2c and produces an output pulse at time tl50 which starts the transmission of samples from port 16 and activates counter 704, which counts down to time t854. illustrated in Figure 2d. Figure 2e illustrates the remaining time up to the next horizontal synchronization mark, which occurs from time t858. The second portion of the quench interval, determined by the duration illustrated in Figure 2e, is 25 4 samples. Figure 2f illustrates a horizontal synchronization signal occurring at a nominal frequency of 15,625 Hz. The calculation duration of the counter 150 is illustrated in Fig. 2g and the calculation duration of the calculator 704 is illustrated in Fig. 2h and ends in the first case at time t854. However, the shutdown interval is now longer and continues from time t854 to time t864, at which time the next horizontal synchronization signal occurs, starting the cycle again.

Since the active time slot in the described system 35 consists of 704 samples, the remainder of the time slot is formed by the quenching portion.

By calculating 150, the calculator 150 generates substantially all of the shutdown intervals that should occur when the system input is a 525/60 input source. Such an input source has a portion of the shutdown interval defined by the counter 150 greater than the portion of the shutdown interval 5 that occurs after time t854 after resetting counter 704 and flip-flop 18 and the subsequent horizontal synchronization pulse time t0. Thus, the first portion of the shutdown interval occurs after each H synchronization pulse and is determined by a counter 150. The second portion of the shutdown interval begins after the active line and continues until the next subsequent H synchronization pulse. As a result, the duration of the second portion of the shutdown interval that occurs within each line varies with the duration of the horizontal line-15, which is determined by the standards of the supply source.

The significance of the number 704 is based on the fact that the factors 704 have several 2 powers (704 = 2 ^ x 11) and as a result there may be six 20 levels of hierarchy in the device. Furthermore, 704 samples per line allow the shutdown interval to occur in the 625/50 system and is extremely close to the defined limits of the NTSC shutdown interval.

The arrangement of Figure 1 illustrates a digital signal processing system according to the invention, in which the synchronization source may correspond to either the 625/50 or 525/60 standard and in which the input signal is analog. In many cases, however, it may be desirable to transfer-encode from another digital system to the standards described in connection with the arrangement of Figure 1. In the example case, it has been mentioned that in the United States and possibly other countries, it may be desirable to use a digital video system in which the standard clock frequency is based on a multiple of 35 subcarrier frequencies, being e.g. 4 x SC. As will be described, the number 704 is also advantageous in that it provided easy transmission coding between such a combined digital NTSC standard and the general or global standard described in connection with Figure 1.

5 In a combined NTSC television signal sampled at 4 x SC, 910 samples appear during each full horizontal line. However, 754 of the samples occur during the active portion, while the remaining 156 samples occur during the quench intervals 10. In order to implement transfer coding in accordance with another aspect of the present invention, 748 samples are required per active portion of each line. This number 748 is chosen because it has a common factor of 44 (748 = 17 x 44) over the number of samples in the global system 15 (704 = 16 x 44). This means that each horizontal line in either system can be divided into 44 transmission coding blocks, each containing 17 samples per block in the second case, while in the other case there are 16 samples per block. Figure 3 20 helps to illustrate this situation. The horizontal axis of Figure 3 represents time. The length of the line in Figure 3b is 16 units, each character representing a sample time. The 16 samples shown in block 3b correspond to a batch of 44 similar blocks that may occur sequentially during each active portion of each horizontal line in the global digital standard. The block of samples illustrated in Figure 3a is located in approximately the same time portion as the block illustrated in Figure 3b. However, in the block of samples 30 in Figure 3a, there are 17 samples instead of 16. Nevertheless, it is to be understood that 44 blocks of samples such as those shown in Figure 3a occur within the same time period as 44 blocks of samples shown in Figure 3b. When the total number of samples is selected so that they cannot be divided into relatively small blocks, the amount of signal processing required for transmission coding may be greatly reduced. Assuming that digital signals are available sampled at the frequency illustrated in Figure 3a, it is apparent that a certain amount of interpolation is required to generate a signal according to the clock control system shown in Figure 5b. For example, the seventh sample of Figure 3b is located approximately midway between the seventh and eighth samples of Figure 3b. As a result, the value of the sample 10 of the seventh 3b can be approximated by the average of the signals from the seventh and eighth sample points of the incoming signal, which signal is clock-controlled as in Fig. 3a. Similarly, the second sample of Figure 3b (sample sequence number is 1) is very close to the second sample of Figure 3a (sample sequence number is one) and its value can be taken to be approximately equal to the signal value in sample 1 of Figure 3a plus 1/16 of the difference between samples. the sequence number is one and two, between the values. In general, the value of n linearly 20 interpolated output samples is determined by the equation g 'from the equation »' n- £ n + Γ6 <*„ «- V (1> where n may vary from 0 to 16 and represents the sample number of the new samples to be formed. The transfer coding criterion according to the invention uses the fact that the coefficient 17/16 is a ratio of small integers and that the denominator of the ratio is the power of the second.

According to the waveform f (t) of Fig. 4, a series of sample values can be denoted by f, occurring at a frequency of 4 x SC, denoted as a frequency of F 1. The straight lines connecting successive sample values represent a linear approximation of the analog waveform f (t) and the samples labeled g 'represent interpolated _____ n_ ---- i2 73853 samples at a clock frequency of 13.5 MHz (F2>. Measure defined by Equation 1). consists of two additions and one multiplication.One of the factors of multiplication is the fraction n / 16, where n is a small integer.Although electronic multiplication of binary numbers is a complex and time-consuming operation, division by two can be easily accomplished by shifting one bit in the shift register. a binary number, e.g., 234 ^ = HIOIOK ^, can be divided by two yk-10 by simply appending zero to the left most significant bit and deleting the least significant bit, resulting in 011101012 = 117 ^, which is half of the previous number to 7 bits to the original eight bits compared to the accuracy of multiplying the value of the sample by a multiplier, in Example 7/16, can be accomplished by dividing the original sample value S four times in succession by 2 to give 8 / 16S, 4 / 16S, 2 / 16S, and 1 / 6S of the original sample value, respectively. Then 7/16 times 20 this value is obtained by adding together the values obtained from the performances 4/16 S + 2/16 S + 1/16 S, performing two consecutive additions. Thus, any number in digital form can be multiplied by a factor of n / 16, performing four consecutive transfers and up to three consecutive additions. This procedure is generalizable to any multiplication operation made with ice n / 2r, whatever the integer r then was.

Linear quantization according to the above method may generate errors during interpolation. The error of Fig. 4 corresponds to the difference between the value of the curved waveform f (t) at time n between the sampling point g 'and the point of the straight line 410, the straight line being between the points fn + 1 and fn. This error may be small, especially when the result of the interpolation is tied to the same number of levels as the input waveform. Errors tend to be highest sisääntu-levan waveform to the maximum curvature points and they are directed in the direction of the curvature of the inside. Such 5 errors do not occur in flat (constant plane) or linearly changing areas of the image, but only occur in the vicinity of a variable slope (curved downward or upward). Thus, interpolation errors occur only at high definition points or at 10 rapidly changing edges. The subjective effect of the error is to reduce the curvature or soften the outline of the image.

Interpolation errors from the curvatures of the analogous approximation f (t) from which the initial sample values f were formed can be significantly reduced by using information obtained from multiple surrounding points, such as using three or four samples instead of two. This can be accomplished by using extensions 412 and 414 of the straight-line determinations formed between the sample points f1 and fR and the points fn + 1 and fn + 2, respectively. Bearing in mind that the temporal occurrence of new samples g 'at F2 may be very close to the sampling time f at the beginning of the sample block 25 or very close to the sample time f ^ at the end of the sample block, it is obvious that the weightings given to approximations g "or g"' the actual value of gn at a given time n depends on the temporal proximity of sample gn to either sample f 30 or f From Figures 3 and 4 it should be noted that each new sample value gn within a given block of samples can be directly derived from existing sample f and hence numbering of new samples gn according to Figure 4 shown corresponds to the numbering of old or incoming samples 35 f, n 14 73853

The value of the point g "is equal to the known value of the incoming samples f plus the incremental fraction of the difference between samples f and f, since this incremental rate nn-1 is the same whether it is between samples n-1 and n or between samples n and between n + 1.

Thus, 9 ”= f + Te (f - f J (2) ^ nn 16 n n-1 10 Similarly, the value of the point g" 'with the extension 414 can be determined by adding to the known value the difference between the sample values and fn + 2 multiplied by the number obtained by subtracting of one is the increment used to define g "n and therefore holds 15 9 · '„ * fn + l <fn + l - fn + 2> <3>

It is obvious that when the new sample g is close to n times fn, g "n can be added in a certain way, weighting it to the value defined for the quantity g ', in order to form an approximation, if g is close to fn + i, to add a value of g "'weighted in a certain way to the value of g'.

A good approximation for the new sample value gn is 25 with gn being closer to the point f (when n = 0.1, ...

7) 16-n M n i t ..

gn »-g” n + - g'n (4) n 16 n 16 30 and when the quantity gn is closer to the point f ^ (when n = 9, 10, 11, ... 15) it is _ n «I 16 * n * i, iq = - g "'+ ------ q * (5) n 16 n 16 n 35 15 73853

For the case n = 8, the values from Equations (4) and (5) are averaged to give g8 = 2 (2 g "8 + 2 g" '8 + gV (6) 5

It can be seen that Equations (4), (5) and (6) are the sums of the inputs, where the inputs are of the form K / 16 g. As a result, the square-law or parabolic approximations for the values of the function f (t) gn can be realized by dividing by a second and performing addition operations, as was also the case with linear interpolation.

Due to the curvature of the curve f (t) below the rectangular tangent of the curve f (t) at point f, the terpolated value of gn in-15 between points g 'and g "n near the center of time interval n and n + 1 is probably slightly larger than what is f (t) the actual value before it was sampled to generate the values of f. Thus, the errors made by the described square wave interpolation procedure are in a direction that tends to enhance changes that subjectively affect the enhancement of transition points, or edges, in the television image.

Figure 5 illustrates an arrangement for performing square law interpolation according to the described method. In Fig. 5, the clock frequencies generated by the clock generator 502 and F 2 relate to each other as

Fl 2r + l Τ 'm r (7) 2 2 30 which, as described, provides a desirable property that divides the sampling times in each line into interpolation blocks or groups with coincident samples at each end of the group. The combination of analog color television signals f (t) is input to a sampler 504, which sequentially samples the incoming analog signal and holds the samples for a time sufficient for the ADC 506 to quantize the samples to M bits per sample. As is known, M bits may occur simultaneously on parallel conductors 5 or in series on a single conductor. Each M-bit sample represents one sample value f. The various samples f (such as samples f η, f, f., F _) are stored in the register 508 after pe-n ni nn * rl n * ^, from which they are available, so that different approximations g'n, g "n can be calculated. , 10 g "'and finally g.

n n

The synchronization of the different calculations within the sample blocks is realized by horizontal synchronization signals obtained by a separator 512 from the analog input signal f (t). The separated sync-15 signals include H sync, shutdown, reconstructed color subcarrier, and corresponding signals. The synchronization signals are input to a synchronizer, illustrated as block 526, which sends a color subcarrier-based signal to the clock signal generator 502, 20 to lock the sampling clock frequency to 4 x SC. The synchronization block 526 also receives a signal indicating the full number of counts from the N, r-degree counter 510 to reset this counter. The synchronization block 526 also delays the operation of the counter 510 from 25 until the start of the active portion of each horizontal line. In the arrangement of Figure 5, it is assumed that the sampling frequencies have been selected, as previously described, according to a global digital standard to facilitate transmission coding by interpolating 30 sampling frequencies based on 4x SC, so that the number r in equation (7) is known and may be a value such as r = 4 to obtain repetitive interpolation blocks with a length of 16 new samples gn and 17 old samples fn · A counter 510 35 is connected to receive block start signals 17 73853 from the synchronizer 526 and repeatedly counts clock pulses and provides a digital parallel to the conductor 514 a signal representing the current value of the number n, which in the example case may vary from 50 to 15. The counter 510 is reset, as mentioned, by a synchronizer after each full periodic count n = N. The prevailing value of n in conductor 514 is brought to a comparison table 516, which is indicated by a signal in conductor 514. At each memory location, va-10 is marked with information about which of the samples near f is used for calculation with that value of n. This information is input to a calculation processor 518, which calculates g'n, g "n and g" ', as defined by the stored instructions in Table 516, for the value of n according to Equations (1), (2) 15 and (3). These calculations are performed, as described, sequentially by dividing the different f values by 2 and summing the quotients of the different divisions according to the stored instructions.

Rounding errors can be minimized by performing a two-partition shift shift and summing in chip registers with (M + r) bits. The values g ', g ", and nng"' n computed in section 518 are sequentially input to inventory register 520 and are still available in calculation circuit 522, where the value of 25 gn is computed according to instructions from register 516 for that value of n by performing equations (4), (5), and ( 6). After calculating g, the least significant bits are removed to return to the M bit output, and gn is loaded into buffer 524. The interpolated signals are clocked out of buffer 524 at frequency F2 and form a transmission coded signal.

It will be apparent to those skilled in the art that the global standard component system may use YIQ; Y, (B-Y), (R-Y) or other components instead of the listed RGB. It is also apparent that the duration of the shutdown interval determined by the counter 150 is adjustable relative to the desired duration and location synchronization.

The interpolation arrangement described so far focuses on transfer coding by interpolating the signals, the signals being related to each other in the sampling frequency ratio F ^ / F2 = M / Sr, where M = (2r + 1), whereby Fj frequency samples gradually shift over the interval between successive F ^ samples , as illustrated in Figure 3, over the duration of one block of samples. In the specific example described, the frequency ratio F 1 / F 2 is determined by the ratio 4 x SC / 13.5 MHz, which is in fact equal to the ratio 35/33 and approximately equal to the ratio 17/16, so that it corresponds to equation (7) for the value 15 r = 4. This allows the advantage of interpolation by successive shifts and addition. The advantages of interpolation by transfer and addition are not limited to the case where the denominator differs from the numerator by a unit integer, but can be implemented for any positive integers M and r whenever the numbers M and 2r have no common factor.

By transmitting PAL signals with 625 lines in the picture and a frame rate of 50 Hz to the proposed global 13.5 MHz standard, it can be implemented by interpolation according to this additional method, and then a reduced interpolation error can be achieved.

As shown in Fig. 4, the interpolated value for the new sample gn in the left half of the time interval n and n + 1 is determined as follows. 30 First, the incoming samples f and fn + ^ occur at times n and n + 1, respectively. Second, amplitude differences are defined, between fn_ ^ and fn, between f and fn + ^. Third, amplitude differences are weighted according to the relative temporal position of the samples within a given sample block. Fourth, each weight

II

19 73853 to form a linearly interpolated sample between n f and fn + i and to form a second sample linearly extrapolated from the region between fn_ ^ and fn. The linearly interpolated and extra-5 polished values are then further weighted according to their proximity to point f and added together to form the interpolated value. In the second, i.e. right-hand half, in the time interval between n and n + 1, a corresponding procedure diagram is implemented for the points f ^, fn + j 3a ^ n + 2 su ^. Thus, the interpolation scheme described in connection with Figure 4 uses three samples of the incoming signal to determine the value of each interpolated sample. It is also possible to simultaneously utilize four incoming sample points to form an improved interpolation for any positive integers M and r, as mentioned.

A generalized transmission coding procedure scheme using any positive integer M and r is useful, for example, for chip coding of 625/50 PAL 20 cases into 13.5 MHz sampled signals conforming to the above-mentioned proposed global standard. For this transmission coding, the PAL signal can be sampled at a frequency of 4 x SC, so that 1135.0064 samples are obtained for each full horizontal line. It is already known that these samples can be smoothed or reduced to exactly 1135 samples per field and the resulting error is only 0.16% skew in image geometry.

The ratio of 1135 samples per PAL line to the Earth-30 weather standard 864 samples per line is 1135/864 = 1.3136574. This figure is very close to the quotient 21/16 = 1.3125. As a result, the active line of 704 samples in the 13.5 MHz world standard can be filled with 4 x SC PAL samples by converting 21 input-35 input samples at 4 x SC into a total of 16 output samples at 13.5 MHz in each sample group. 2ο 73853 π :: - - in size, giving exactly 44 blocks in the area of the active image. The result of the approximations included in such transfer coding is a geometric accuracy of 5 (12/16) (864/1135) = 0.9991186 which represents a geometric distortion in the form of elongation of less than 0.1 percent. Image processing that results in vertical or horizontal distortion below the 1% level should generally be considered acceptable because it is close to the tolerance limit at which cameras and picture tubes can be aligned. The distortion brought about by the approximations included in the transfer coding is much smaller than this limit 15 and is acceptable.

Within each chip coding block, when converting an NTSC case to a world standard, there is, as already described above, the gR position of each new sample as it shifts over the time interval between incoming samples by more than 20 regularly propagating variables. At the beginning of each block, gn occurs simultaneously with f, and as time increases, it shifts partially over or between successive samples f and fn + ^ until, at the end of the sample transfer coding block, gn occurs simultaneously with fn. This 25 regular shift is due to the extra one in the numerator of Equation (7). This numerator is denoted by M. In the case of PAL, the symbol differs from the denominator by more than one unit. In particular, in the case of transfer coding the PAL standard to the world standard 30, the quotient can be formed in the form P1 _ M _ 2r + 5 21 F2 2r 2r "16 * ö 'where the numerator M is 21 and differs from the denominator value by 16 to 35 units. the physical significance of the difference 21 7385 3 is that there are 21 samples of the incoming signal within each transmission coding block during the time period in which 16 new transmission coded samples are generated.This arrangement is illustrated in Figure 6. As in Figure 5, the length of line b represents the duration of one interpreter block. and is divided into 16 stations representing sampling times.Dots a represent the sampling times of the incoming signal.The difference M - 2r has a second physical meaning corresponding to the first 10. This second meaning can be explained in connection with Figure 6 by stating that each new sample ( the point on line b) in Figure 6 is located between the input samples (a) in time k (M-2r) / 16 or 5/16 of the time interval between samples compared to the previous position.

15 For example, sampling points 0 occur simultaneously, new (b) sample point 1 occurs 5/16 of the distance between incoming (a) sample points 1 and 2, new point 2 occurs 5/16 + 5/16 = 10/16 of the distance (a) sample points 2 and 3. Correspondingly, a new point 20 3 occurs in time 15/16 of the distance between points 3 and 4 of the incoming sample, a new point 4 occurs at (15/16 + 5/16) -1 = 20/16 - 16/16 = 4/16 of the incoming: the duration between samples 5 and 6. The new or outgoing sample 5 occurs at 4/16 + 5/16 = 9/16 between incoming samples 6 and 7 and the new sample 6 occurs at time 9/16 + 5/16 = 14/16 from the incoming samples 7 and 8. between. Figure 7 lists all the stations shown in Figure 6. No new samples are located between incoming samples 4 and 5, 8 and 9, 12 and 30 13, and 16 and 17. Figure 15 lists the corresponding information for transmission coding, where r = 4 and M = 25.

The interpolations described in connection with Figure 4, when generating an approximation gn (new value under assessment), use g "n weighted by a certain first set of functions-35 in the first half of the 22 7 3 8 5 3 interval between consecutive input samples f and use a second weighting function in the second half of this interval. This provides an interpolation that may be acceptable in certain situations, but better approximation of 5 (lower error) can be achieved by taking the weighted average of g'n, g "n and g" 'n over the entire time interval between samples. 1/2 (g '+ -2 -—- g "+ - g"' (9) 'n 9 n, r ^ n 9r yn 10 t where further n * = / (M-2r) xn / (modulo 2r ) (10) 15 The physical significance of the large n 'is given to the position of the new samples b compared to the incoming samples a. In Figure 6, n' = (21-16) n modulo 16 = 5n modulo 16 (11) 20, which means that for each new sample n for n 'the value increases by 5/16 part, as already mentioned. (As is known, modulo k means the remainder obtained by dividing the above number by the divisor k).

The approximation of Equation 12 to the quantity gn as illustrated in Figure 8 represents a parabola passing through the points f and fn + ^. As illustrated, the parabola is sharper than what would be a third-order curve passing through the four points f fn, 30, and f ». my

An alternative interpolation scheme is illustrated in Figure 9. A particular first parabola 900 is passed through the points fn_1, fn and fR + 1 and a second parabola 902 is passed through the points f, fn + 1 fn + 2.

35 These curves can be defined by the following equations: (23) gn = 1/2 (2r + n, g '+ 2r-n' g ") (12) 5 (902) g_ = 1/2 (2r + ln 'q'_ + n' q "\.) (13) n - n - n 2r 2r

When interpolating a new sample gn between the time fR of the sample and the time n + 1 of the sample f ^, as already mentioned and described, Equation (12) in the first half of the time interval and Equation (13) in the second half and the average of the two can be used. at a point in between. On the other hand, the average over the whole time interval gives the equation 15 gn = 1/4 (3 g '+ 2r-n1 g "n = n» g "') (14) 2r 2r

Another approximation to the value of gn of the new sample interpolated to the interval f-20 of successive samples can be accomplished by weighting Equation (12) more strongly near the beginning of the time interval and weighting Equation (13) more strongly near the end of the time interval, giving the equation 25 gn = 2r- n '(equation (12) + nV (equation 13) (15) 2r 2r

Figure 10 generally illustrates the difference between the gn values of the new samples as determined by the approximations of the interpolation 30 described by Equation (9) and Equation (14). The solid line 1009 has the shape of a parabola according to Equation 9 and the dashed line curve 1014 has the shape of a parabola according to Equation 14. Curve 1009 is relatively sharply curved, falling below points f and fn + 2 -35 le, while curve 1014 is less sharply curved and is located above these points. It has already been mentioned the fact that interpolation can be arranged to make the transitions more efficient and thus to provide an image with a "softer" or "steeper" appearance. It is clear from Figure 10 that interpolation using Equation 9 provides new samples that enhance the steepness in the regions of steep curvature compared to those obtained according to Equation 14.

Equations 4-6 and 9-14 represent interpolations of square law (or 10 higher order) with uniform features of passing through points f and f ^ and representing the sums or income of multiplication operations from the four sampling points f. , f, f.

n-x n 11 + x and fn + 2 and where the multipliers are of the form p / 2r, 15 where p is an integer varying between zero and 3Γ + 1 2. Thus, with an embodiment of the invention, these algorithms can be implemented with a series of transfer operations and additions that can be easily implemented in a high-speed format.

The circuit arrangement of Figure 11 can be used to implement a common type of transmission coding, as described above. Figure 11 shows the parts corresponding; case of Figure 5, are denoted by the same reference numerals.

F2 ~ frequency clock pulses are collected in an r-degree n-count-25 m 510, which is reset by the timing controller 1104 when the final count number 2r-1 is reached (in the case of PAL, reset to 15). For each value of n, from the r-degree calculator 510, the ROM reference register 516 selects the appropriate instructions to calculate the values of g'n, g "n, and g" 'based on the current f values stored in the memory register 508.

Figure 12 is a more detailed block diagram of an embodiment of a general transmission encoder applied to transmit encoding PAL-35 signals sampled at 4 x SC (approximately 17.7 MHz) to 13.4 MHz. The analog PAL composite signal f (t) is applied via input terminal 1210 to the prefilter, 17.7 MHz sampler, and ADC device illustrated as block 1212. The output of block 1212 is a series (in this case 8) of parallel 5 spurious signal transmission channels in their conductors, one representing the least significant bit (LSB) and the other the most significant bit (MSB). The signals of these conductors are introduced in parallel or simultaneously into an equal number of shift registers in block 1214. Only the shift registers of the LSB and MSB signals are illustrated in block 1214. The clock control of shift registers 1214 is controlled by timing signals in addition to the clock pulses, certain synchronization information regarding the incoming PAL signal so that the processing of the incoming signals can be synchronized so that it occurs as transmission coding blocks starting with the active video portion. The newest 20 signals of the shift registers correspond to fn + 2 and the oldest to f and f and fn + ^ are at certain intermediate locations. These 8-bit signals are input from shift registers 1214 and applied to the inputs of pairwise differentiating circuits 1218, 1220 and 1222. Thus f and f. 25 is fed to circuit 1218, fn + 1 and f are fed to circuit 1220, and fn + 1 and ^ n + 2 are fed to circuit 1222. The differentiating circuits also receive timing inputs (T) from the timing control circuit 1216 to synchronize circuit operation with the samples. The outputs from the differentiating circuits 301818 and 1220 are applied to the inputs of the multipliers 1224 and 1226, respectively, which multiply by the number n '/ 16, as described, by performing successive divisions and additions depending on the values of the continuous variable n' entered from the ROM comparison table 1228. As mentioned, n 'represents the temporal location of the new sample to be formed relative to the times of the adjacent incoming 26 73853 samples. For a given transmission coding, such as in the case of the PAL format to the 13.5 MHz format, the frequency ratio is known and as a result n 'direct correspondence to the sample number is known, as shown in the example table shown in Fig. 7. The ROM 1228 is assigned information based on the clock frequency F2 of the new sample, calculated by the calculator 1230 into blocks of n parts. Each memory location thus assigned has already been previously entered with information 10 related to the value n 'and corresponding to the address number n for this particular transmission coding. Thus, for each new sample generated within the transfer coding block, the multipliers 1224 and 1226 receive from the ROM memory 1228 a suitable n 'value indicating the summations to be performed on the difference signals divided by two.

The output signal from the multiplier 1226 is input to the multiplier 1232, where it is computed with the current value of one f to provide a linearly interpolated sample g'n, as described in Equation (1). Accordingly, an output signal is applied from the multiplier 1224 to the clock-controlled summing circuit 1234, where it is summed with f to provide a linearly extra-polished sample g "n according to Equation (2). The current value of n '25 is input from ROM 1228 (16-n1) -differentiation to the input 1235 and the difference signal is applied to the input of the multiplier 1238. The difference signal ^ η + ι “^ η + 2 ^ · j ° ^ a generated by the differential circuit 1222 is applied to the second input of the multiplier 1238. depending on the value of (16-n '), generating an input signal which is input to the summing element 1240 to be summed with the value of fn + ^ to form g "' according to Equation (3).

35 The value of g is now introduced into the addition circuit 1244 via a new multiplier 1242. The multiplier 1242 27 7 3 8 5 3 multiplies by a constant value 11/16, which is also of the form n / 16 and can therefore be implemented by second divisible circuits and adders. These values of g "n and g" 'are weighted according to the position gn of the new sample compared to the incoming samples of the adjacent si-5 by multipliers 1246 and 1248, respectively.

The multiplier 1248 multiplies by the number n '/ 16 and receives from the ROM 1228 the value of the continuous variable n' for this task. The multiplier 1246 multiplies by the number (16-n) / 16 10 and receives as a continuous variable a difference signal from the (16-n) isolation circuit 1236. Both of these multipliers are a desirable type of high transfer and summation implementation, described below. These weighted g "n and g" 'n signals are summed in the summing circuit 1550. The output signal of the summing element 1250 is the sum of the small portion g "n and the large portion g"' when n 'is small, i.e., when the new sample gn is close sample fn ·

When the new sample gn is close to fn + ^, that is, when n 'is close to 16, the signal provided by the summation member 2050 is generated from the large portion g "n and the small portion g" 1 signals. This weighting provides an estimated value of f (t), which analog input signal is particularly curved or enhanced in curved areas. In order to "tint" the peak formation, the output of the adder 1250 is multiplied. the summed signal by a fixed factor of 15/16 in the multiplier 1252, thus reducing the weighting of the approximate approximation compared to the linear estimate g'n · The adder 1244 adds 11/16-weighted g'n and 5/16-weighted g'n and the g "'n signals and output are rounded to obtain a new estimated gnvalue.

It is now apparent that the value of the weighting of the signals in the multipliers 1242 and 1252 is freely variable so as to provide the desired level of enhancement. The Te-35 host effect can be included in the algorithm, ____________ n_ .. __ - 28 7 3 8 5 3 by which new samples are formed: g = g '+ - (2 · g "+ - g"') (16) yn 2r yn 2r 2r * n 2r yn 5 where k is a steepness constant, which may be zero or a certain positive value up to its maximum value 2. When k = 0, one of the previous terms is zero and the in-terpolated value of gn is merely the linear interpolation of equation (1) g'n · The proportion of the right-hand term of equation (16) within the parentheses 10 represents a parabola corresponding to fR and fn + ^ values, but with a steeper curvature than would be expected in the input signal f (t). As the constant k varies from zero to 2r, Equation (16) varies through all possible parabolas passing through the points fR and f ^ and located between the straight line g 'and the very sharp parabola that is equal to (16). ) within parentheses. In the example case, the value k (8) gives equation (9) and when k = 4 we get equation (14). In Figure 12, the value of the constant k is included by means of fixed constant multipliers 1242 and 1252. The multiplier 1242 multiplies by the number (16-k) / 16 and the multiplier 1252 multiplies by the number k / 16, where k = 5, and the transmission encoder generally operates according to Equation (16).

The multipliers 1224, 1226, 1238, 1246, and 1248 multiply the continuous variable divided by the number 2r by the quotient, where r = 4 and 2r = 16. The multipliers 1242 and 1252 have the same shape but have a fixed numerator. Fig. 13 illustrates in the form of a block diagram a digital arrangement for dividing the input signal X by a number 30 of the form 2r and multiplying the result by a variable indicated by p. Fig. 13 introduces a continuously variable factor p to the input terminal 1310 as a multiplier and multiplies X by input. is introduced (in series or in parallel) into register 1322, in which, as illustrated, 29 73 85 3 an 8-bit digital word 10000001 is entered, which has a representative value of 129. The most significant bit of register 1322 represents 128. Dividing by two is performed by entering the contents of register 1322 into another 9 -bit register to the last eight 5 degrees. The most significant bit of register 1324 also represents a value 128 and is pre-entered with a value of zero. As a result, moving the number 10000001 from register 1322 to register 1324 represents a second division. The value stored in the 9-bit register 1324 is shifted to the last nine stages of the 10-bit register 1326, where 128 values are pre-entered in the most significant bit position. As a result, the transfer of data from register 1324 to register 1325 still represents a new second division. The data is further distributed by performing successive transfers to the 11-bit register 1328 and the 12-bit register 1330. At the end of the transfers, 1324, 1326, 1328 and 1330 are entered with X / 2, X / 4, X / 8 and X / 16, respectively. Noting that these components represent 8/16 · Χ, 4/16-X, 2 / 16'X and 1/16 · Χ values, respectively, it is apparent that any X fractional value between 1/16 and 15/16 is available in different as the sum of the combinations of distribution values stored in these registers. In the illustrated example case, the number p has a value of 7 (as digital 0111): and as a result, the contents of registers 1326, 1328, and 1330 must be added together to obtain the sum 7/16-X. The value of the number p is read into the memory 1332. The contents of each step of the register 1332 are used to adjust the gate control of the registers 1324-1330 implemented at gates 1334-1340. The value of one at a certain degree in register 1332, sal-30, corresponds to the summing of registers 1324-1330 to the post-register aggregation circuits. Registers 1324 and 1326 are connected to the inputs of the summing circuit 1324 and registers 1328 and 1330 are connected to the inputs of the summing circuit 1344. The outputs of the summing circuits 1342 and 1344 are fed to the input of a further summing circuit 1346 30 73853, where the final output signal (p / 16 * X) is generated. The blocks illustrated next to summers 1342, 1344, and 1346 illustrate the digital values of these points.

Although the embodiments described so far take advantage of transfer and addition multiplication, it is possible to use interpolators according to the more general form of Figure 14. The sampling frequencies for the input and output signals are selected such that when -10 when there are an integer number of transmission coding blocks within the active line at the beginning and end of each transmission coding block with simultaneous input and output times. Such interpolators are advantageous compared to the prior art, even if 15 standard multipliers are used, because a few such multipliers are needed to implement the given accuracy. For example, the interpolator of Figure 14 with four multipliers corresponds to a previously known arrangement with as many as 15 multipliers.

In Fig. 14, an input signal is applied through an input terminal 1410 to the inputs of a delay section 1412 and a synchronization or timing circuit 1424. The delay section 1412 delays the signal by a known amount to provide a delayed signal fR defining the input signal f. The delayed signal f is applied to still other delay sections 1414 and 1416 to provide further delayed signals fn + 1 and fn + 2. The signals £ ^, £ „, fn + 1 and fn + 2 are applied to multipliers, such as standard 8x8 multipliers, to multiply the signals by a known function 30 (obtained from the ROM 1420 of the comparison table) of a variable variable n formed by synchronization or at multiplier 1424. The multiplied signals are computed in summing section 1432 to provide the desired interpolated output signal to output terminal 1422.

Instead of using a ROM memory table, 31 73853 such as ROM 1228 in Figure 12 to provide an n 'value of the number n according to the known temporal location of the new samples between the time instants f of adjacent incoming samples for a certain general transmission coding, it is also possible to use a logic circuit which calculates the number n 'from the number n according to the following equation n' = (M-2r) xn (modulo 2r) 10

Figure 16 illustrates such a logic circuit.

In Fig. 16, the input clock signals are input at an output or new clock frequency F2 to an r-degree n-counter 1230 corresponding to the device of Fig. 12. These F2 clock-15 signals are also applied to the timing control circuit illustrated as block 1616, which provides reset pulses to counter 1230 and n 'to counter 1618 when the F2 frequency clock pulse is counted to read 2r by counter 1230. This resets counters 1230 and 1618 each. at the beginning of the block of renewable samples. The calculator 1230 calculates the F2 clock pulses, determining the value of the current number n, i.e. the number of the output sample within each interpolation block. The calculation amount currently stored in register 1230 is 13 (= 1101) in illustration case. With each successive F2 clock pulse, the timing controller 1616 controls a clock-controlled adder 1620 that adds n 'to register 1618 to the currently stored n' value (which in the illustrated case was at its previous or previous n 'value 13 or 1101) a fixed number 30 (M- 2r), which in the illustrated case is 5 (= 0101).

The sum of the two is stored in register 1622, which has r + 1 degrees, of which the leftmost degree is most significant. The sumam of the numbers 5 and the previous value 13 for the value n 'is 18, i.e. 10010, which is currently shown stored in the register 1622. All r significant degrees of register 1622 are connected to the corresponding degrees of register 1618 to update the value of n 'to its current number. However, since only the least significant bits of register 1622 are switched-5 ty, only these are stored in register 1618 as a new n 'value. This arrangement causes the value of n 'to advance by five unit quantities (M-2r) for each n count until the sum exceeds the value of (2r-1), with the most significant bit in degree (r + 1) of register 1622 moving to logical 1 state. . The transfer of these r least significant bits allows the transfer of five transfer rates in the manner of modulo 2 operations.

Although the embodiments described so far are suitable for interpolation between signal samples relative to horizontal scan lines in a digital television system, it should be apparent to one skilled in the art that the same methods of interpolation can be applied for interpolation between signals having different frame rates between the equal pay samples in the images.

Claims (25)

33 73853 A sampling system for a television signal, the system comprising a clock signal generator 5 for generating clock signals at a frequency of 13.5 MHz + n · 2.25 MHz (n = 0.1 ...) and a sampling device connected to said clock signal generator and a source of television signals for sampling television signals, characterized by selection means (16, 10 18, 150, 704) for selecting a fixed number of samples from the horizontal lines of at least one component of the television signals, said fixed number of samples being from a portion of the television signal occurring during the active horizontal line interval but not including samples occur after the start of the horizontal synchronization pulse in the inactive part of a given horizontal line, and wherein said fixed amount includes a large number of coefficients of 2. A system according to claim 1, characterized in that the source of the television signals (10) is a source of baseband television signals. A system according to claim 1, characterized in that the selection means (16, 18, 150, 704) comprise an adjustable gate means (16, 18). A system according to claim 3, characterized in that the selection means (16, 18, 150, 704) further comprise calculating means (704) connected to the adjustable port means (16) for limiting the number of samples to be taken from the television signals to said fixed amount. A system according to claim 1, characterized by digital signal processing means (16-24, 150, 704) for digitally processing said component at a sampling frequency of 13.5 MHz. A system according to claim 1, characterized in that said fixed amount is the product of a multiplier 44 x 16, i.e. 704. A system according to claim 5, characterized in that the digital signal processing means (16-24, 150, 704) comprise an adjusted port 5 means (16, 18, 150, 704) for excluding a certain number of samples present in each after the start of the horizontal synchronization pulse in the inactive part of each horizontal line, and which passes through said fixed number of samples. A system according to claim 6, characterized in that there are 858 samples per line in 525 line images transmitted at a rate of 30 frames per second, and in that there are 864 samples per line in 625 line images transmitted at a frequency of 25 frames per second. A system according to claim 1, characterized in that the selection means (16, 18, 150, 704) comprise a gate (16). A system according to claim 1, characterized in that the selection means (16, 18, 150, 704) comprise means (150) for setting the switch-off interval. A system according to claim 10, characterized in that the means (150) for To set 25, it comprises a calculator (150). A system according to claim 11, characterized in that the counter (150) is activated by H-synchronization. A system according to claim 12, characterized in that the counter (150) counts on a predetermined amount selected to concentrate said fixed amount, which includes a plurality of coefficients of 2. A receiver for digital television signals sampled at 13.5 MHz, the receiver comprising a digital signal processor, 73853 35 receiving said samples and characterized in that the signal processor processes said signals in a form having an even number N active samples per horizontal line, where N is the product of multiplication 5 P times Q, P is the second plural integer power, and Q is an integer close to 44, and that the receiver comprises digital / analog signal processing means for generating analog signals for the processed TV. signals. 15. A receiver for digital television signals, the receiver comprising a source of digital signals sampled at 13.5 MHz, digital signal processing means coupled to the signal source for processing the signals, and 15 digital / analog converter means coupled to the digital signal processing means. output for generating an analog signal for television, characterized in that the source of the digital signals produces an even number N of active samples per horizontal line, where N is the product of multiplication P times Q, P is the second plural integer power and Q is an integer with value is close to 44. Receiver according to Claim 14 or 15, characterized in that P has a value of 16. A receiver according to claim 14, 15 or 16, characterized in that said number of N active samples is selected for suitable transcoding from an NTSC or PAL composite signal sampled M times during each active portion of the horizontal line of said composite signal, wherein M is the product of the multiplication R times Q and the difference D between P and R is a small integer. A receiver according to claim 17, characterized in that the value of D is one for the NTSC signal. 36 73853 Receiver according to Claim 17, characterized in that the value of D is for five PAL signals. 20. A digital color television transmission system, characterized in that for suitable code conversion, a standard television video signal sampled at a frequency which is the product of a small integer and a color subcarrier frequency of said standard television video signal is provided: a sampled television-video signal is formed, to select from the active portion of each horizontal line of the sampled television video signal, where M is the product of an integer R and an integer Q, where the value of the integer R is close to 16 and the value of the integer Q is close to 44, and the clock signal generator frequency is 13.5 MHz. to generate clock signals as sampling signals for said digital transmission system with an even number N of said clock signals occurring during each time interval of said M samples-20, where N is the product of multiplication P times Q, P is the second the plural integer power of n and the difference D between P and R is a small integer. System according to Claim 20, characterized in that D is the one .. A system according to claim 21, characterized in that P is 16 and R is 17. A system according to claim 20, characterized in that D is five. A system according to claim 23, characterized in that P is 16 and R is 21. A system according to claim 20, characterized in that M is close to 748. 37 73853