CA1203314A - Compatible, transcodeable, and hierarchical digital tv system - Google Patents

Abstract

-20- RCA 76,709 ABSTRACT OF THE DISCLOSURE
A digital television system in which signals are sampled at 13.5 MHz and produce an integer number of samples during each horizontal line interval whether the signals are based upon PAL/SECAM or NTSC standards.
In order to make the digital system hierarchical and to adapt it for simple transcoding from an NTSC signal sampled at 4 times color subcarrier, the number of samples occurring during the active portion of each horizontal line is made equal to 704. Transcoding by interpolation from 4XSC - sampled NTSC video to the digital system is accomplished by selecting a particular number of samples per active line such that small blocks of samples can be transcoded independently, which allows interpolation to be achieved simply.

Description

~2~:3 3~

- 1 - RC~ 76,709 This invention relates to a digital television syster;l which is compatible with the most widely-used worldwide television standards, and to arrangements for ready transcodiny between video signals sampled at various rates.
~arious characteristics of a worldwide standard for compatible digital television have been considerec1. It has variously been suggested that there should be an equal number of sar.lples during the total duration of a horizontal line in both 525-line 60-hertz (N'rSC) and 625-line 50-hertz (PAL/S~C~q) systerls, or

2~ possibly an equal number of samples during the active portion of each line. AIso among the issues relating to such a worldwide standard are t:he sampling frequency appropriate for limited bandwidth systems and yet having adequate resolution, and whether the standard should be a composite luminance-chro~inance system as opposeo. to component systems such as RGB or YI~.
It is also desirable to have a digital television standard which is hierarchical. A hierarch~cal system is one in which various grades or levels of

3~ detail or service can be simply transmitted, as by filtering and deleting samples r Thus, a digital system might allow for generation of signals at a very high sample rate providing resolution suitable for cinema-type use. Such a resolution might be 2000 lines per raster vertically and 2000 television lines horizon-tally.
Television production houses might for editing purposes wish to use a resolution greater than the standard television resolution but ~ight wish to use equipr.~ent less costly than that capable of operating-at data ra-tes q~ ~

~2~33~

- 2 - RCA 76,70 commensurate with a 2000-line raster. Thus, -the television production house might use equipment capable of using the second level of the hierarchy, which is lO00-line resolution. If a tape recording originally made at the 2000-line resolution level were available to the production house, ~iltering and deleting alternate samples of each line would reduce the resolution to the lO00-line level. The next level in the hierarchy might ~e 500-line resolution, which might be used in a television broadcast station for generating analog video for transmission to homes. A tape edited by a television production house could be used by the broadcaster in equipment capable of 500-line resolution by deleting every other sample. Alternatively, the television station could use a 2000-line resolution tape by dele-ting 3 samples out of 4. The next step in the hierarchy might be appli.cable to electronic newsgathering cameras at 250-line resolution, and the next lower level of resolution might be used for surveillance purposes.
It is commonly expected that in the United States and in other countries using NTSC standards that equipment will be commonly available for processing television signals in a composite form. It is highly advantageous in such equipment to have the sampliny rate an integer multiple such as 3 or ~ times the color subcarrier frequency (3XSC, 4XSC). It seems very likely that the world standard for digital television when it is ultimate].y adopted will not be based on a sampling rate lockecl to a color subcarrier. However, it is very desirable that subcarrier-locked sampled composite video be easi].y transcodeable to have the charac-teristics of the standard when that standard is adopted. In all likelihood, this transcoding will require in-terpolation ~ 33~
- 3 - RCA 76,709 of the values of the samples in the world standard from the values o~ the neares-t adjacent samples of the composite NTSC video. Naturally, if the clock rates were identical, the samples would be identical and no interpolation would be necessary. Exact interpolation is complex and requires multiplications and additions for each interpolated sample. ~ultipliers especially tend to be slow in operation and in order to achieve operation at high video data rates they may be expected to be expensive. It would be highly desirable to have a worldwide television standard for digital video which is compatible between the 625/50 and 525/60 standards as to sampling frequency, which is hieraxchical and which is also readily transcodeable from composite NTSC video sampled at a multiple of the subcarrier rate without the use of multipliers.
The original NTSC standard horizontal line frequency for monochrome television was 15,750 hertz.
With the adoption of color systems the line rate was changed to be related to the sound subcarrier frequency of 4.5 MHz. The exact horizontal line rate is 1/286 X 4.5 MHz, which the CCIR has standardized to 2.~ 15734.264 ~ 0.0003% Hz. More recently, the FCC has defined the color subcarrier frequency in megahertz as the quotient 315/88, and the line rate is 2/455 times that subcarrier frequency which is approxima-tely 15,734.266. rn the 625/50 standard, the horizontal line rate is 15,625 hertz.
It is known -that a common clock frequency of precisely 13.5 ~Hz provides exactly 864 samples per horizontal line in the 625/50 system and tha-t it provides exactly 858 samples per line in the 525/60 system.
Thus, sampling rates of 13.5 MHz (and other sampling frequencies related thereto by multiples of 2.25 MHz) provide integer numbers of samples per line in bo-th systems.

~2~)3~
~ 4 - ~CA 76,709 The duration of the horizontal line in a ~5/50 system is 64.00~S, and in the 525/6~ system the duration is approximately 63~56 ~S. The CCIR standards for the 625/50 system provides for an active line duration of approximately 5~ microseconds with a blanki~g duration of 12 microseconds. The blanking duration according to present NTSC color standards is 10.9 ~ 0.2 ~S, but proposals have been made for change -of this standard. Thus, the blan~ing duration in NTSC
is not clearly defined. If it is assumed that the active line duration in 525/60 is also 52 ~S, the 13.5 MHz sample rate yields 702 samples for the active portion of each line. The nu~ber of samples occurring during the blanking portion, however, varies fro~ 162 in the 625/50 system to 156 in the 525/60 system.

XO Summary of the Invention According to the present invention, with a sampling frequency of 13.5MHz (or other sampling frequency related thereto by a multiple of 2.25MHz), the number of samples for the active portion of each 2~ line is sel~ted for instance, by a counter-controlled gate, to be a number rich in powers of 2, such as 16, thereby facilitating the provision of a hierarchical system. To facilitate transcoding, as will be explained, it is also advantageous for the number of active samples 80 q to be:lr~ltiple of a factor near 44, such a nurrker appropriate for a 13.5MHz sampling rate being 704, which is 16 x 4a. The be~efits which can follow from such selection of nurnerical parameters will be further described with reference to the accompanying drawings, which also illustrate various 36 forms of apparatus presenting or taking advantage of these benefits.

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-5- RCA 76,709 1 DESCRIPTION OF THE DRAWING~
FIGVRE 1 is a block diagram of a television system including a digital portion in accordance with one aspect of the in~ention;
FIGURE 2 illustrates timing signals useful in understanding certain aspects of the arrangement of FIC,URE l;
FIGURE 3 is a timing diagram useful in understanding the relative sampling times when 10 transcoding from NTSC composite color television signals to signals according to the standards of the arrangement of FIGURE l;
FIGURE 4 illustrates a generalized waveform aiding in understanding the errors arising upon 15 transcoding by interpolation at the new sample points of the values of the signal as originally sampled; and FIGURE 5 i~ a functional block diagram of an embodiment of the invention involving transcoding.
FIGURE 6 is a timing diagram us2ful in understa~ding the relative sampling times when transcoding from PAL signals to signals according to the standards of the arrangement of FIGVRE l;
FIGURE 7 is a tape listing interpolation weighting factors for PAL transcoding;
~ IGURES 8, 9 and 10 are generalized waveforms aiding in understanding the errors arising upon transcoding by interpolation in a general manner;
FIGURE ll is a block diagram illustrating 30 generalized interpolator similar to the interpolation of FIGURE 5.

3314!~

1 - 6 - RCA 76,709 E~IGURE 12 is a more detailed block diagram of a generali.zed interpolator adapted for enhanced interpolation of signals in a PAL - 13.5 MHz transcoding;
FIGURE 13 iS a block diagram of a digital arrangement for dividing an input signal ~ by a number of the form 2r and multiplving the result by a running variable p.
FIGURE 14 is a block diagram of a generalized interpolator according to an aspect of -the invention;
FIGURE 15 lists the n to n' translation for a particular transcoding; and FIGURE 16 is a block diagram of an alternative embodiment of a n to n' translator.

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~L2~13~

1 ~ 7 - RC~ 76,709 DESCRIPTION OF THE INVENTION
FIGURE 1 illustrates an arrangemen-t in accordance with the invention. In FIGURE 1, analog red (R), green (G) and blue (B) signals, -together with horizontal synchronizing signals (H) are provided from a source (not shown) such as a television camera. The H signal is applied to the enable input of a counter 150,while the R, G and B signals on their separate lines are applied to an appropriate anti-alias prefilter 10 where the bandwidth is limited to prevent -the appearance oE aliases in the output signal. The band-limited R, G and B siynals are applied to an analog-to-digital converter (ADC) 12 within which -the separate R, G and B
signals are sampled and quantized at a 13.5 MHz rate under the control of a clock signal applied -thereto from a clock generatox 14. ADC 12 may generate the R, G and B signals at its output terminals in the form of multiple parallel channels for each signal or as a single serial channel for each signal. In the illustrated embodiment, 8 parallel lines are used for each signal.
The signals are applied from ADC 12 to a gate 16 which can be enabled by a flip-flop 18 to allow 2~ samples to pass or which can prevent the passage of samples to ~urther digital signal processing illustrated as a block 20. The digital signal processing 20 forms no part of the invention and is some function which it is desirable to perform in a digital mode. For example, the digital signal processing may include tape recording, -tape editing, color control or blending or other special effects. Also, digital signal processing could simply be a transmission channel by which the digital signals are sent to a distant location. After signal processing, the signals need no longer be in digi-tal form and are therefore applied to a digital-to-analog converter (DAC) 22 where quasi-analog samples are generated. The quasi-analog signals produced thereby ~0 33~

- 8 - RCA 76,703 are applied to an equalizing filter 24 for fil-tering or smoothing to produce appropriate analog video.
In aecordance with one aspect of the invention, gate 16 is enabled to define the active line and eon-trolled so as to allow preeisely 704 samples to flow through tne digital signal proeessor 20 durinq each active line. The timing control required is providecl by a flip-flop (FF) 18, counter 150 10 and eounter 704. X sync signals 204 defining the beginning of each horizontal line are applied to the enable input of eounter 150,-to ano-ther input of which are applied 13.5 MHz eloek signals from generator 14.
Counter 150eounts 150clock or sample pulses, and produces at the end of -this -time interval an output pulse which is applied to the reset input of eounter 150, to the enable input terminal of counter 704 and to the set input terminal of FF 18 to eause the Q
ou-tput of the FF to yo high to enable gate 16 to begin to pass samples. Counter 704 begins to count in synehronism wi'ch the samples flowing through yate 16 and when preeisely 704 samples have been counted, eounter 704 produees an output signal whieh resets eounter 704 and whieh is also applied to the reset inpu-t of FF 18 to reset the Q outpu-t to zero to thereby disable gate 16 and prevent khe passage of further samples,thus defining the end of -the active intervaL
The operation of the timing arrangement of FIGURE 1 and the differenees between 525/60 and 625/50 operation are more elearly shown in FIGURE 2. In FIGURE 2a, clock samples 202 are illustrated, not to scale. In FIGURE 2b, hori~ontal sync pulses 204 are illustratecl which are at a 15734.266 nom.inal rate.
Beginning at time tO eorresponding to the beginning of a hori~ontal line, counter150 coun-ts until time tl50 as illustra-tecl in FIGURE 2c and produces an output pulse at time tl50 which begins the gating of samples through gate.16 and enables eounter 704 whieh coun-ts until -time t854 as illustrated in FIGURE 2d. FIGURE 2e ~L26~3~
- 9 - RCA 76,709 illustrates the remaining time until the next following horizontal sync signal which occurs beginning at -time t858. The second part of the blanking interval, defined by the duration illustrated in FIGURE 2e, is 4 samples.
FIGURE 2f illustrates horizontal sync signals occurring at a nominal ra-te of 15,625 hertz. The dura-tion of count of counter 150 is illustrated in FIGURE 2g and the duration of count of coun-ter 704 is illustrated in FIGURE 2h and terminates as in the first case at time t854. However, the blanking interval is now longer and extends from -time t854 -to time t864 at which time the next horizontal sync signal occurs to begin the 1~ cyele again.
5ince the aetive interval in the deseribed system is definecl by 704 samples, the remainder of the interval is by definition blanking. The 150-count of eounter 150defines substantially all of the b:Lanking interval whieh would oceur when the system input is from a 525/60 source. With such a souree, that portion of the blanking interval defined by the 150-eounter is larger than that portion of the blan~ing interval occurring after the time t854 of 25 resetting of counter 704 and FF 18 and the time tO of the next following horizontal sync pulse. Thus, the first portion of the blanking interval occurs after each H sync pulse, and is defined by counter i50. The seeond part of the blanking interval begins after the aetive line and extends until the next following H
sync pulse. Consequently, the duration of -the second portion of the blanking interval which occurs during each line will vary depending upon the dura-tion of a horizontal line as defined by the source standards.
The signifieance of the number 704 is derived from the fact that 704 is rich in powers of 2 (704 = 26 X 11) and consequently, it can support 6 levels of hierarchy. Furthermore, 704 samples per line allows the blanking intervals for the 625/50 system 3~
1 - 10 - RCA 76,709 to be met and is extremely close to -the specified limits of the NTSC blanking interval.
The arrangement of FIGURE 1 illustrates a diyital signal processiny system according to thé
invention in which -the source synchroniza-tion may correspond to either a 625/50 or a 525/60 standard and in which the input signal is analog. However, in many cases it may be desirable to -transcode from another digital system into the standards described in conjunction with the arrangement of E'IGURE 1. For example, it has been mentioned that in the United States and possibly in other countries it may be desirable to have a system of digital video in which the standard clocking rate is based upon a multiple of the subcarrier rate, such as 4XSC. As will be described, the number 704 is also advantageous in that it allows for easy transcoding hetween such a composite NTSC
digital standard and the general or world s-tandard described in conjunction with FIGURE' 1.
In a composite NTSC television signal sampled at 4XSC, 910 samples occur during each complete horizontal line. ~owever, 754 of the samples occur durina the 2~ active portion while the remaining 156 occur during the l~lanking intervals. In order to accomplish transcoding according to another aspect of the invention, 748 samples per active portion of each line are required.
The number 748 is chosen because it has a common factor 30 of 44 (748 = 17 X 44) ~ith the number of samples in the world system (704 = 16 X 44). This means that each horizontal line of either system can be divided into 44 trans-coding blocks, one of which wili contain 17 samples per block while the other contains 16 samples per block. FIGU~E 3 35 aids in visualizing this scheme. The horizontal axis in FIGURE 3 represents -tlme. The length of the line in FIGURE 3b is 16 units long, with each mark representing a sample time. The 16 samples shown in the block of FIGURE 3b correspond to one o~ 44 similar ~2~33~
I

~ RCA 76,709 blocks which rnay occur sequentially during the active portion of a horizontal line in the world digital standaxd. The block of samples illustrated in FIGURE 3a occupies approxima-tely the same time duration as does the b~ck illustrated in FIGURE 3b. ~owever, the block of samples of FIGU~E 3a has 17 samples rather than 16.
Nevertheless, i-t will be understood that 4~ blocks of samples such as shown in FIGURE 3a will occur within the same time as 44 blocks of those shown in FIGURE 3b.
By selecting the total number of samPles so that they can be divided into relatively small blocks, the amount of signal processing necessary for transcoding may be much reduced. Assuming that digital signals are available sampled at the ra-te illustrated in FIGURE 3a, it will be apparent that to generate a siynal according to the clocking sys-tem of FIGURE 3b some lnterpolation will be required. For example, the seventh sample in FIGURE 3b lies approximately half-way between the seventh and eighth samples in FIGURE 3a.
Consequently, the value of the seventh 3b sample can be approximated by the average of the values of the signal at the seventh and eighth sample points of the incoming signal clocked as in 3a. Similarly, the second sample (sample number one) of FIGURE 3b lies very close to the second sample (sample n~lmber one) in FIGURE 3a, and its value may be estimated to be equal -to the signal value at sample 1 of FIGURE 3a plus 1/16th of the difference between the values at sample number one and two. Generally speaking, the value g' of the n-th linear interpolated output sample is determined by gn fn ~ 16 (fn+l fn) (1) where n may range from 0 to 16 and represents the sample number of the new samples being generated The transcoding aspect of the invention uses the fact that the factor 17/16 is the ratio of small in-tegers, and that the denominator of the ratio is a power of 2.
In accordance with -the waveform f(t) of 0 ~2~33~
1 - 12 - RCA 76,709 FIGURE 4, le-t fn be the sequence of sample values at tne rate of 4~SC which is frequency Fl The straight lines connecting successive sample values represent a linear approximation -to the analog waveform f(t), and the samples marked g'n represent in-terpolated samples a-t the clock rate of 13.5 ~IHz ~F2). The opera-tion defined by equa-tion 1 consists of -two additions and one multiplication. One of the factors in the mul-tiplication is the fraction n/16 where n is a small integer.
Altnougn electronic multiplication of binary numbers is a complex and time consuming operation, division by two is readily accomplisned by moving one bit in a shift register. Any binary number, e.g., 2341o = 111010102 can be divided by two simply by appending a zero on the left of the most significant bit and deleting the least slgnificant bit. The result becomes 011101012 = 1171o which is half of the previous number to 7-bit accuracy for an 8 bit original accuracy. Thus, multiplication of a sample value by a multiplying factor, say 7/16, can be accomplished by dividing the original sample value S four successive times by the integer 2 to get respectively 8/16S,

4/16S, 2/16S, and 1/16S of the original sample value. Then 7/16 times the value is obtained by adding the values obtained for 4/16S + 2/16S + 1/16S in two successive additions. Thus, any number in digital form can be multiplied by the factor n/16 by four successive shifts and up to three successive adds. This technique can be ~0 generalized to any multiplying factor n/2r for any integer r.
Linear approximation by the preceding technique may create errors in the interpolation process. The error in FIGURE 4 is equivalen-t to -the difference be-tween the value of the curving waveform f(t) at the time n of -tne sample poin-t g'n and the point on the straight line 410 between fn+l and fn. This error can be small especially when the interpolated resul-t is quan-tized to the same number of levels as the inpu-t waveform. The ~0 ~2C~3~
.1 - 13 - RCA 76,709 errors -tend to be largest at points of maxir,lum concavity in the incominy waveform and are in the direc-tion toward the inside of the concavi-ty. Such errors do not occur in -flat (constant level) regions of the picture or in linearly changing regions but occur only in the vicinity of changing slope (concave down or concave up).
Thus interpolation errors will occur only in regions of high definition or rapidly changing edges~ The subjective effect of the error is to reduce the concavity, or to soften -the picture edges.
The interpolation error resultiny from concavi-ties in the analog approximation f(t) from which the original sample values fn were derived can be significantly reduced ~y using information drawn from more of the surrounding points, as by using three or four samples instead of two. This is accomplished by using the extensions 412 and 414 of the straight-line 0 approximations formed between sample points fn-1 and fn n~l and fn~2 respecti~ely. Realizing that the time of occurrence n of new samples Yln at the F2 clock rate can occur very near the time of sample fn at the beginning of a block of samples, or very near the time of sample fn+l near the end of a block of samples, it will be apparent that the weight to be given to approximations g"n or g"'n in determining the actual value gn of the new sample at time n will depend upon the proximity in time of sample gn to either sample fn or fn+l I-t should be noted from FIGURE~ 3 and 4 that each new sample value gn within a block of samples is relate~ one-to-one to an existing sample fnr and consequently the numbering of new samples gn as shown in FIGURE 4 corresponds to the numbering of old or incoming samples fn.
The value of g"n equals the known value of incoming samples fn plus an incremental portion of the difference between samples fn and fn-l because that incremental portion is the same whether it is between n-l ~0 9~26~
RCA 76,709 and n or between n and n-~l. Thus g n fn + 16 (frl ~ fn-l) (2) Similarly, the value of g"'n on ex-tension 414 can be determined by adding to the known value of Cn+l the difference in sample values between fn+l and fn+2 multiplied by one minus the incremental portion used to determine g"n, and therefore g n fn+l + 16- (fn+l ~ fn+2) (3) It wil] be apparent that when new sample g is near the time of f , the value of g"n can be added with some weighting to the value determined for g'n in order to form an approximation, and when gn is near the time of fn+l~ the value of g'n can be added with a weighting to the value of g'n.
A good approximation for the new sample value gn when gn is nearer f (when n=0, 1, ...7) is gn -16 g n + 16 g'n (4) 20 and when gn is nearer fn+l (when n=9, 10, 11,... 15) gn 16 g n+ -~- g n (5) For n=8, the results g from equations (4) and (5) are average~ to get g~ = 2 (2 g"8 ~~ 2 g 8 t g 8) (6) - It will be noted that equations (~), (5) and (6) are sums of products, whe:re the products are of the form 16 g. Consequently, the square-law or parabolic approximations gn of function f(t) can be accomplished by successive divide~by-two and summing operations, as in the case of linear interpolation.
Because of the concavity of f(t) below a straight-line tangent to f(t) at point fn the interpolated value of gn between g'n and g"n near the center of the interval between n and n-~l is likely -to be slight:Ly greater than the actual value of f(-t) before it was sampled to produce values fn. Thus, the errors made in -the described square-law interpola-tion process are in a direction which tends to enhance changes, which will have the subjective effect of enhancing - 15 - RCA 76,709 kransi-tions or edges in the television picture.
FlGURE 5 illustrates an arrangement for performing a square-law interpolation in accordance with the described process. In FIGU~E 5, the clock frequencies Fl and F2 generated by clock generator 502 are related by 1 - 2r+1 (7) F2 2r which a$ described yiel.ds the desirable ability to divide the sample times in each line into interpolation blocks or yroups with coincident samples at either end.
Composite analog color television signals f(t) are applied to a sampler 504 which recurrently samples the i.ncoming analog signal and holds the samples for a duration sufficient for ADC 506 to quantize the samples into M bits per sample. As known, the M bits may occur si.multaneously on parallel lines or serially on a single line. Each sample of .~ bits represents one sample value fn. The various samples fn (such as fn-l' fnr fn~l' fn+2) are stored in succession in a reyister 508 where they become available so that the various approximations g'n' g"n' g"'n and ul-timately 'Jn can be calculated.
Synchronization of the various calculations with the blocks of samples is accomplished by horizontal sync signals derived by separator 512 from the analog input signal f(t). The separated sync signals include H sync, blanking, reconstitu-ted color subcarrier and the like. The sync signals are applied to a synchronizer illustrated as a block 526, which transmits a signal related to the color subcarrier to clock signal generator 502 to lock the frequency of sampling clock Fl to.~XS~. Sync block 526 also receives a signal indicative of a full count of ~ from an r-stage counter 510 for resettir~g the counter. Sync block 526 also delays enabling of counter 510 until the beginning of the active portion of each horizontal line. In the ~0 ~3;3~
l - 16 - RCA 76,709 arrangement of FIGURE 5, it has been assumed that the sample rates have been selected as described previously in conjunction with the world digital s-tandard for ease of transcoding by interpolation from a sample rate related to ~XSC, so the number r in equation (7) is known and may be for example a value such as r=~
yielding recurrent in-terpolation blocks of length of 16 10 new samples g and 17 old samples f . Counter 510 is coupled to receive start-of-block signals from synchronizer 526 and recurrently counts E'l clock pulses and produces on a line 514 a parallel digital signal representing the current value of n, which in 1~ the example may range from a value of 0 to a value of Counter 510 is also reset to zero as mentioned by synchronizer 526 after each cyclic full count of n=N. The current value of n on conductor 51~ is applied to a lookup table 516 which is addressed by ~o the signal on line 514. At each memory loca-tion, information is stored as to which samples near fn are to be used for calculation for the particular value of n. This information is coupled to a computation processor 518 in which are calculated Y~n~ g"n and g"n as determined by stored instructions in table 516 for the value of n in accordance with the equations (l)~ (2) and (3). These calculations are performed, as described, by ~uccessive division by 2 of the various values fn and summing of the results of the various divisions according to the stored instructions.
Errors due to rounding-off can be minimized by performing the shifting to accomplish divide-by-two and the additions in shift registers having (~5-~r) bits.
g nl g n and g"n computed in 51~ are successively loaded into a storage regis-ter 520 and are made available -to a further computation circuit 522 where the value of gn is calculated in accordance with instructions from reyister 516 Eor the particular value of n for implementing equations (~), (5) and (6).
~0 l - 17 - RCA 76,709 After compu-t~ion of g , the least significant bits are dropped -to return to an M-bit ou-tput and gn is loaded into a buffer 524. The interpolated signals are clocked ou~ of buffer 524 at frequency F2 and form the transcoded signal.
It will be apparent to those skilled in the art -that the component s~stem for a world standard may use YIQ; Y, (B-Y), (R-Y) or other components rather than RGB as illus-trated. Also, it will be apparent that the duration of the blanking interval defined by counter 150 may be adjusted to the desired duration and position relative to sync.
The interpolation arrangement as so far described relates to transcoding by interpolation of signals related by a sampling frequency ratio Fl/F2=M/2r where M=(2r+1) whereby the F2 samples step progressively across the time separation between successive Fl samples as illustrated in FIGURE 3 over the duration of one block of samples.
In the specific example described, a frequency ratio of F]/F2 is determined by the ratio of 4xSC/13.5 MHz, which i.s actually equal to the ratio 35/33, is approximated by;the ratio 17/16 so as to correspond to equa-tion (7) for a vaIue of r=4. This allows the advantage of interpolation by successive shifting and addition.
The advantages of interpolation by shifting and adding are not limited to the case in which numerator differs from the denor,linator by an integer equal -to unity, but they may be realized for any positive integers M and r, so long as M and 2r have no common ~actor.
Transcoding between PAL signals at 625 lines per frame, 50 Hz frame rate and the 13.5 MHz proposed world standard may be accomplished by interpolation by this additional me-thod and may have reduced interpolation error.

-~ ~z~
1 - 18 - RCA 76,709 As shown in FIGUR~ 4, the interpolated value for a new sample g~ in the left half of -the in-terval between times n and n+l is determined in the following manner. First, incoming samples fn and fn+l occur at times n and n+l respectively. Second, ampli-tude differences are determined: between fn-l and fn; and between fn and fn+l- Third, tne amplitude differences are weighted in accordance with the relative position in time of -the samples in question within a sample block. Fourth, each one of the weighted differences is added to the value of fn to form one sample linearly interpolated between fn and fn-~l and another samplelinearly extrapolated from the region between fn-l and fn. The linearly interpolated and extrapolated samples are then further weighted in accordance with their proximity to fn and summed to produce an interpolated value. In the second or right-hand half of interval n to n+1 a corresponding scheme is applied to 2~ points fn~ fn+l~ and fn+2 Thus, the interpolation scheme described in conjunction with FIGURE 4 uses three samples of the incoming signal to determine each interpolated sample value. It is also possible to ma~e simultaneous use of four incoming sample points in order to achieve improved a5 interpolation for any positive integer M and r, as mentioned.
A generalized transcoding scheme employing any posi-tive integers M and r finds use, for example, when transcoding from 625/50 PAL to 13.5 MHz sampled signals according to the proposed world standard mentioned above.
For this transcoding, the PAL signal can be sampled at 4xSC, to yield 1135.0064 samples for each complete horizontal line. It has been known that these samples can be justified or reduced to exactly 1135 samples per field, and the resulting error is a mere 0.16~ skew in picture geometry.
The ratio of 1135 samples per PAL line to 864 samples per world standard line is the ratio 1135/864 =
1.3136574. This figure is very close to the quotient 21/16 = 1.3125. Consequently, the active line of 704 samples at the world standard 13.5 MHz can - 19 - RCA 76,709 be filled wi-th samples from axSC PAL by converting 21 input samples at 4xSC to 16 output samples at 13.5 M~Iz in each block of samples with precisely 44 blocks over the active picture. The result of the approximations involved in sueh a transcodiny is a geometrie aeeuraey of (12/16)(~64/1135~ = ~.9991186 which represents a geometric distor-tion in the form of a streteh of less than 0.1 pereent. Manipulations of the pieture resulting in vertieal or horizontal distortions of less than 1% are generally eonsidered acceptable, as it is near the limit of tolerance with which eameras and kineseopes ean be aligned. The distortion introduced by the approximations involved in the transeoding is mueh smaller than this limit and is acceptable.
Within each transcoding block of samples involvecl in converting NTSC to world standard, as previously clescribed, the position of each new sample gn stepped aeross the time separation between ineoming samples in a regular progression; at the beginning of each block, gn occurs simultaneously with fn~ and with inereasiny time moves part-way across or between successive samples f and f 1 unti.l at the end of the transeoc~ing bloek of samples, gn oeeurs simultaneously with fn+l This regular progression results from the additional 1 in the numerator of equation (7). This numerator is Called M. In the ease of the PAL
signal, M differs from the denominator by more than unity. In partieular, in the case of transcoding of PAL
-to world standard, the quotient can be formecl F1 = ~1 = 2r+5 ~ 21 (~) F2 ~F 2r 16 where numerator ~l equals 21 and differs from -the value 16 of -the denominator by 5. The physieal meaning of this difference is that within eaeh transeoding block, ~L2C~33~L
1 - 20 - RCA 76,709 21 samples of incoming s:ignal occur within the interval in which 16 new transcoded samples are generated. This arrangement is illustrated in FIGUP~E 6. As in the case of FIGURE 3,the length of line b represents the duration of one interpolation block, and is divided into 16 positions which represent sample times. The dots a represent the sample times of the incominy signal. The difference M-2r has a second physical meaning concomitant with the first. This second meaning may be explained in conjunction with FIGURE 6 by noting that each new sample (those points on line b of F~GURE 6) lies between input samples (a) at a time position which is (~-2r)/16 or 5/16 of an intersample interval from the previous position. For example, sample points 0 occur simultaneously, new (b) sample point 1 occurs 5/16 of the way between incoming (a) sample points 1 and 2, new point 2 occurs 5/16 + 5/16 = 10/16 of the way between (a) sample points 2 and 3. Sirililarly, new point 3 occurs 15/16 of the way between, incoming sample points 3 and 4, new point 4 occurs at a time (15/16 -~ 5/16)-1 = 20/16 - 16/16 = 4/16 along the duratio,n between the times of incorning samples 5 and 6. New or outgoing sample 5 occurs 4/16 + 5/16 = 9/16 between incoming samples 6 and 7, and new sample 6 occurs at a time 9/16 ~ 5/16 = 14/16 between incoming samples 7 and 8.
FIGURE 7 lists all the positions occurring in FIGURE 6.
No new samples lie in the time between incoming samples 4-5; 8-9; 12-13J and 16-17. FIGURE 15 lists equivalent informationfor a transcoding in which r=4, ~=25.
The interpolations described in conjunction with FIGURE 4 when forming an appro~imation for gn(the new value being estimated) use g"n weigh-ted by a firs-t set of functions in the first half of the interval between successive input samples fn and a second weighting function in the second half of the interval. This gives ~Z~33~

- 21 - RCA 76,709 an interpolation which r,1ight be acceptable under some condi-tions, but a better approximation (lower error) may be obtained by taking an average of the weighted estimates g'n, g'ln, and glln over the entirety of each intersample interval. Such an average is g = 1/2(g'n + 2r-n' g'ln + n' g n ) (9) n 2r 2r where n' = l(~-2r)xn~(modulo 2r) (10) The physical meaning of n' relates to the position of new samples b relative to incoming samples a.
In FIGURE 6~
n' = (21-16)n modulo 16 = 5n modu]o 16 (11) which means that for each new sample n, the value of n ï increases by 5 parts out of 16, as mentioned.
The approximation -to gn of equa-tion 12 as illustrated in FIGURE ~ represents a parabola which passes through the points fn~ fn+l As illustrated, the parabola is more peaked than would be a third-order curve passing through the four points fn l~ f~ f~
:en-~2 An alternative interpo~atlon scher,te is illustrated in FIGURE 9. A first parabola 900 is passed through points fn-1~ fn and fn+l~ and a seco 30 parabola 902 is passed through points fn~ fn+l and fn-~2-These can be defined by the following equations:
(900) gn = l/2(2r+n' s'n + 2r~n' g"n)(12) (902) gn = 1/2(2r-~1-n s'n + n' g 'n) (13) When interpolating a new sample gn between the times n of sample fn and time n-~l of sample fn+l' ~2~;~3~
1 - 22 - RC~ 76,709 one coulcl as previously described use equation (12) in the first half of the interval and equation (13) in the second half, with the average of the two at the intermediate point. The average over the entire interval, on the other hand, gives the equation gn = 1/4(3 g n ~ 22rn g n 2r (14) Still another approximation for the value of new sample gn interpolated between successive samples fn can be made by weighting equation (12) more heavily near the beginning of the interval and weighting equation (13) more heavily near the end of the interval, 1~ -the equation for which is gn = 2r-n' (equation 12) + n' (equation 13) (15) FIGURE 10 illustrates generally the differences between the values of new samples gn as determined by 20 the interpolation approximations described by equation (9) and equation (14). Solid curve 1009 has the shape of a parabola according to equation 9, and dashed curve 1014 has the shape of a parabola in accordance with equation 14. Curve 1009 is relatively sharply curved, falling below points ~n 1 and fn~2 whereas curve 1014 is less sharply curved and lies above these points.
r~entiOn has been made of the fact tha-t an interpolation may be arranged to provide enhancemen-t of transi-tions and thereby provide a pic-ture having a less "soft" or '7 more "crisp'7 appearance. It is clear from FIGURE 10 that interpolation by use of equation 9 will provide new samples which enhance crispness in regions of sharp concavity by comparison with those established according to equation 14.
Equations 4-6 and 9-14 represent square-law (or higher-order) interpolations which have the common features of passing through points fn and En+l and which represent the sums of multiplications or products of Eour sample points fn 1' fn/ fn+l and fn~2 and in which ~L2~)33~L
- 23 - RCA 76,709 the multipliers take the form p/2r where p is an inteyer ranging bet~;/een the values of zero and 2r~l. The embodiment oE the invention can therefore implement these algorithms by a succession of shifts and adds, which are easily implemented in a high-speed form.
A circuit arrangement as in FIGURE 11 may be used to implement a transcoding of general type as describecl above. In FIGURE 11, elements corresponding to those of FIGURE 5 are designated by the same reference numbers. Clock pulses at the F2 rate are accumulated in an r-stage n-counter 510 which is reset to zero by timing control 110~ when -the final count of 2r-1 is reached (in the PAL example, reset at 15). For each value of n from r-stage counter 510, ROM instructions register 516 selects the appropriate instructions for calculation g n' g n' and g n from the currently stored values of fn in storage register 508.
FIGURE 12 is a more detai:Led block diagram of an embodiment of a generalized transcoder adapted for transcoding of PAL signals samp:Led at 4xSC (about 17.7 MHz) to 13.5 r~Hz. Analog PAL composite sicJnal f(-t) is applied by ~ay of input terminal 1210 to a prefilter 17.7 r~Hz sampler and ADC illustrated as a block 1212.
Sampling within block 1212 is controlled by the Fl clock.
The output of block 1212 is a plurality (in this case 8) of parallel signal-carrying channels on lines 7 one of which represents a least-significant bit (LSB) and another the most siynifiean-t bit (~ISB). The signals on these lines are applied in parallel or simultaneously to a like plurality of shift registers within a block 1214.
Only the shift registers for the LSB and MSB signals are illustrated within block 1214. Cloc};ing of shift registers 1214 is controlled by timing signals produced by a timing control circuitry illustrated as a block 1216. Timing circuitry 1216 receives, in addition to Fl clock pulses,certain sync information ~33~
- 2~ - RCA 76,709 rela-ting to the incoming PAL signal so that the processing of the incoming signals may be synchronized so as to occur in transcoding blocks beginning with the ac'cive video. The newest signals in the shift registers correspond to fn+2 and the oldest to fn-l~ with fn and f +l at intermediate locations. These 8-bit signals are coupled from shift registers 1214 and applied in pairs to the inputs of differencing circuits 1218, 1220, and 1222. Thus, fn- and fn-l are applied to 1218; fn~l and fn are applied to 1220; and fn+l and f +2 are applied to 1222. The differencing circui-ts also receive timing (T) inputs from timing control 1216 to synchronize their operation with the samples.
The outputs of the differencing circuits 1218 and 1220 are applied to -the inputs of multipliers 1224 and 1226, respectively, which multiply by n'/16 as described by successive divisions-by-two and additions, depending upon the values of running variable n' applied thereto by Ror~q look-up table 1228. As mentioned, n' represents the time position of the new sample belng generated relative to the times of the adjacent incoming samples.
For a given transcodiny as :Erom PAL to 13.5 MHz, the frequency ratio is known and therefore the one-to-one correspondence of n' to the sample number is known, as given for example in the -table of FIGURE 7. ROM 1228 is addressed by information related to new sample clock frequency F2 counted by a counter 1230 into blocks n.
Each memory location so addressed was previously loaded with inforr,lationrelating to the value of n' corresponding to the address number n for -that particular transcoding. Thus, for each new sample being genera-ted within a transcoding block, multipliers 122~ and 1226 receive from ROM 1228 a suitable value of n' indicative of the addi-tions which mus-t be made of -the divided-by-two difference signals.

~0 ~61 3~
- 25 - RCA 76,709 The output signal from multiplier 1226 is applied to an adder 1232 in which i-t is sumrned with the current value Of fn to produce a linearly interpola-ted sample g'n as described by equation (1). Similarly, the output signal from mul-tiplier 1224 is applied to a cloc~ed adder circuit 1234 where it is summecl with f to produce a linearly extrapolated sample g"n according to equation (2). The current n' value is applied from ROM 122a to a (16-n') differencing circuit 1235, and the difference signal is applied to an input of a multiplier 1238. The difference signal (fn~l~fn+2) produced by difference circuit 1222 is applied to a second input of multiplier 1238.
Multiplier 1238 forms a product by successively dividing-by-two and adding depending upon the value of (16-n') to form a product signal which is applied to an adder 1240 for summing with the value of fn~l to form g''n per equation (3).
The g'n value is applied by way of a further multiplier 1242 to a summing circuit 1244. Multiplier 1242 multiplies by a constant value 11/16, which is of the Eorm n/16 and therefore may be implemented by divide-by--two circuits and adders. The g"n and g'~'n values are weighted by multipliers 1246 and 1248 respectively, in accordance with the position of new sample gn relative to the ad]acent incoming samples.
Multiplier 1248 multiplies by n'/16 and receives from ROM 1228 running variable n' for this purpose. ~ultiplier 1246 multiplies by (16-n)/16 and receives as a running variable -the difference signal (16-n) from differencing circuit 1236. soth of these mul-tipliers are of the desirable high-speed shift-and-add types as described below. These weigh-ted g"n and g"'n signals are added in a summing circuit 1250. At -the ~33~
- 26 - RCA 76,709 OUtpllt of summer 1250 the signal is the sum of a smal].
por-tion of g"n and a large portion of g'~'n where n' is small, which is to say when new sample gn is near sample fn~ When new sample gn is near fn+l that is when n' is near 16, on the o-ther hand, the signal produced by summer 1250 is formed by a large proportion of g"n and little from g'~'n This weighting creates an estima-ted value of f(t), the analog lnput signal which is very peaked or enhanced in areas of curvature. In order to "tone down"
the peaking, the summed signal at the output of summer 1250 is multiplied by a fixed factor 15/16 in a multiplier circuit 1252 t thereby reducing the weight accorded to the peaked estimate compared with linear estimate g'n.
The 11/16 weighted g'n and 5/16 weighted g"n; g'~'n signals are summed together in summer 12~4 and the output is rounded to produce -the new estima-ted value gn.
It will be apparent -that the value of the weiyhting of -the signals by multipliers 1242 and 1252 may be varied at will so as to provide the desired degree of enhancement. The enhancement effect may be incorpora-tecl into the algorithm by wnich the new samples are formed:
g = 2r-k s'n + k (2r-n' gn" + n' gn'r') (16) n _ 2r 2r- 2r where k is a crispening constant which may be zero or a positive value up to its maximum value of 2r. When k=0, 30 the second term becomes zero and the interpolated value f gn is merely the linear interpolation g'n Of equation (].). The portion of right-~ancl term of equation (16) within the parenthesis represents a parabola which matches the values of fn and f"+l, but which has a much sharper 35 curvature than would be expected from the input signal f(t).
As k ranges :Erom zero to 2r, equation (16) ranges through all possible parabolas that pass -through the values fn and fn~l and lie between -the straigh-t line g'n and the very sharp parabola within the paren-thesis of equation (16).
~0 ~(3 33~
1 - 27 - RCA 76,709 A value k=8 ~or example yields equation (9), and a value of k=4 yieids e~uation (14). In FIGURE 12, the value o~ k is included through fixed-constant multipliers 1242 and 1252. Multiplier 1242 mul-tiplies by 16-k and multiplier 1252 multiplies by k/16 where 16 k=5 and the transcoder operates generally in accordance with equation (16).
10Multipliers 1224, 1226, 1238, 1246, and 1248 multiply by the quotient o~ a running variable divideu by 2r, where r=4 and 2r=16. Multipliers 1242 and 1252 have the same forrn but have a fixed-value numerator.
FIGU~E 13 illustrates in block diagram form a digital arrangement for dividing an input signal X by a number of the form 2r and multiplying the result by a running variable designated p. In FIGURE 13, the running variable multiplier p i5 applied to an input terminal 1310 and multiplicand Xis applied to an input terminal 1320.
Multiplicand X is applied (in series or in parallel) to a register 1322 which as illustrated is loaded with an ~-bit digital word 10000001, representing the value 129. The ~SB of regis-ter 1322 represents a value 128. Division by two is accomplished by loading the contents of register 1322 into the last 8 stayes of a 9-bit second register 1324. The MS~ of regis-ter 1324 also represents the value 128, and is preloaded with the value zero. Consequently, the transfer of 10000001, from regis-ter 1322 to register 1324 represen-ts a division-by-two. The value stored in 9-bit register 1324 is transferred to the last 9 stages of 10-bit register 1326, the MSB of which is preloaded with -the value o~ 128. Consequently, the transfer of da-ta from register 1324 to 1325 represents a further division-by-two.
The data is further divided by successive transfer -to ll-bit register 1328 and 12-bit register 1330. A-t -the end o~ the transfers, registers 1324, 1326, 1328 and 1330 are loaded with X/2, X/4, X/8, and X/16 respec-tively.
No-ting that these components represent 8/16X, 4/l~X, ~Z~33~
- 28 - - RCA 76,709 2/16X and 1/16Y respectively, it is apparent that any fractional value of X from 1/16 to 15/16 can be obtained as the sum of various combinations of the divided values stored on the registers. In -the example illustrated, p has a value of 7 (digital 0111) and therefore the contents of registers 1326, 1328 and 1330 must be summed to produce a sum of 7/16X. The value of p is read into a register 1332. The contents of each stage of register 1332 is used to control the gating of registers 1324-1330 as represented by gates 1334-1340. A value of one in a stage of register 1332 allows the corresponding 15 one of registers 1324-1330 to be gated to further sumr.ling circuits. Registers 132~ and 1326 are coupled to inputs of a summing circuit 1342, and the registers 1328 and 1330 are coupled to the inputs of a summing circuit 13a,4. The outputs of summing circuits 1342 20 and 1344 are coupled to the input of a further summing circuit 1346 where the -final output signal (p/16X) is formed.
The blocks illustrated adjacent to summers 1342, 1344 and 1346 illustrate the digital values at those points.
While the embodiments so far described use 25 the advantages of multiplication by shift-and-add, interpolators of the moregeneral form of FIGURE 14 are possible. The sample rates of the input and output signals are selec-ted so that an integer number of transcoding blocks occur during each active line, with 30 simultaneous input and output sample times at the beginning and end of each transcoding block. Such interpolators are advantageous by comparison with the prior art even though standard multipliers are used, because few such multipliers are necessary to achieve 35 a given accuracy. For example, -the interpolator of FIGURE 14 having 4 multipliers corresponds to a prior-art arrangement having as many as 15 multipliers.

~v ~ ~I
- 29 - RCA ~6,709 In FIGURE 14, an input signal is applied by way of inpu-t terminal 1410 to the inputs of a aelay element 1412, and a sync or timing circuit 1~24. Delay element 1412 delays the signal by a known amount to produce a delayed signal f which defines the input signal as fn 1 Delayed signal fn is applied to further delay elements la~l~ and 1416 to produce further delayed signals fn+l and fn~2- signals fn_l~ fn~ fn+l~
fn~2 are applied to multipliers which may be standard 8~8 multipliers for multiplying the signals by a known function (obtained from table look-up ROM 1420) of the running variable n which is generated by a sync or timing circuit 1424. The multiplied signals are summed in an addex 1432 to produce the desired interpolated output signal at output terrninal 1422.
Rather than using a ROM table look-up such 20 as RO~-~ 122~ of FIGURE 12 to generate the value of n' from the value o n in accordance with the known pattern of the location in time o new samples gn between the times of adjacen-t incoming samples fn Eor a given general transcoding, it is posslble to use a logic circuit to calculate n' from n according to the equation.
n' = (M~2r) x n(modulo 2r) FIGURE 16 illustrates such a logic circuit.
In FIGUR~ 16, input clock signals at the output or new clock frequency F2 are applied to an r-s-tage n-counter 1230 corresponding to that of FIGUR~ 12.
The F2 clock signals are also applied to a timing control circuit illustrated as a block 1616 which generates rese-t pulses for counter 1230 and for a n' counter 1618 at the completion of a count of 2r F2 clock pulses by counter 1230. This resets counters 1230 and 161~ at the beginning of each recurrent block of samples.
Counter 1230 counts F2 clock pulses to cletermine the ~L2~
1 - 30 - RC~ 76,709 current values of n, the output sample number within each interpolation block. The count currently stored in register 1230 as illustrated is 13 (1101).
At each successlve F2 clock pulse, timing control 1616 drives a clocked adder 1620 which adds to the value of n' currently stored in n' register 1618 (as illustrated the last or previous value of n' was 13 or 1101) a fixed number ~M-2r) which as illustrated is 5 (0101).
The sum of the two is stored in a register 1622 having r~l stages of which the left-hand stage is the most significant. I'he sum of 5 and the previous value 13 of n' is 18 or 10010, shown as being currently stored in register 1622. The r least significant stages of register 1622 are coupled to corresponding stages of register 1618 for updating the value of n' to the current value. However, because on].y the LSB of register 1622 are coupled, only these are stored in register 1618 as the new n'. This arrangement causes the value of n' to progress in units of Eive (~-2r) for each count of n until the sum exceeds the value (2r-1), at which time the Mss i,n the (r~l) stage oE register 1622 is toggled as to a logic 1 state. ~he transfer of the r LSB allows progression by steps of five in modulo 2r fashion.
While the er;~bodiments so far described apply to interpolation between signal samples along the hori~ontal scanning lines in a digital television system, it should be apparent to those skilled in the ar-t that the same interpolation methods can be applied vertically to adjacent signal samples in successive lines for interpolation between signals of different line scanning rates, or in time between cosited samples in successive frames for interpolation between signals at different frame rates.

Claims (26)

-31- RCA 76,709 What is claimed is:

1. A television signal sampling system, comprising:
a source of composite television signals;
clock signal generating means for generating clock signals at a sampling rate of 13.5MHz + n x 2.25 MHz, wheren=0,1....;
means coupled to said clock signal generating means and to said source of television signals for sampling said television signals; and selecting means for selecting from horizontal lines of at least a component of said composite television signals a fixed number of samples, wherein said fixed number of samples are from that portion of the TV signal occurring during the active horizontal line interval but not including samples occurring after the beginning of the horizontal synchronizing pulse in the non-active portion of a given horizontal line, and wherein said fixed number is rich in factors of 2.

2. A system according to claim 1 wherein said fixed number is an integer multiple of 16.

3. A system according to claim 1 or 2 wherein said fixed number has a factor which has a integer value near 44.

4. A system according to claim 1 wherein said sampling rate is 13.5 MHz and said fixed number is 704.

5. A system according to claim 1 wherein said source of television signals is a source of baseband signals.

6. A system according to claim 1 wherein said selecting means comprises controllable gate means.

-32- RCA 76,709

7. A system according to Claim 6 wherein said selecting means further comprises counting means coupled to said controllable gate means for limiting the number of samples from said television signals to said fixed number.

8. A system according to claim 6 or 7 wherein said controlled gate means operates on digital samples for excluding a particular number of digital samples occurring after the beginning of each horizontal synchronizing pulse in the non-active portion of each horizontal line and for including a said fixed number of digital samples.

9. A system according to claim 1, 2 or 4 further comprising digital signal processing means for digitally processing said component at said sampling rate.

10. A system according 10 claim 1 wherein said selecting means comprises means setting a blanking interval.

11. A system according to Claim 10 wherein said means for setting said blanking interval comprises a counter.

12. A system according to claim 11 wherein said counter is enabled by the horizontal synchronizing pulse.

13. A receiver for digital television signals sampled at 13.5 MHz, the receiver comprising digital signal processing means coupled to a source of said digital signals for processing said signals in a format having an even number N of active samples per horizontal line where N is the multiplicative product of P times Q, P is a plural integer power of two and -33- RCA 76,709 Q is an integer having a value near 44; and digital-to-analog conversion means coupled to the output of said digital signal processing means for generating an analog signal for television.

14. A receiver for digital signals for tele-vision, comprising;
a source of digital signals sampled at 13.5 MHz and having an even number N of active samples per horizontal line where N is the multiplicative product of P times Q, P is a plural integer power of two, Q is an integer having a value near 44;
digital signal processing means coupled to said source of signals for processing said signals; and digital-to-analog conversion means coupled to the output of said digital signal processing means for generating an analog signal for television.

15. A receiver according to claim 13 or 14 wherein P has a value of 16.

16. A receiver according to claim 13, wherein said number N of active samples is selected for convenient transcoding from an NTSC or PAL composite signal sampled at M times during the active portion of each horizontal line of said composite signal, where M
is the product of R times Q, and the difference D
between P and R is a small integer.

17. A receiver according to claim 16 wherein the value of D is unity for an NTSC signal.

18. A receiver according to claim 16 wherein the value of D is five for a PAL signal.

-34- RCA 76,709

19. A digital color television transmission system adapted for convenient transcoding from a standard television video signal sampled at a rate which is the product of a small integer and the rate of the color subcarrier of said standard television video signal to thereby form a sampled television video signal, said system comprising:
selecting means for selecting M samples within the active portion of each horizontal line of said sampled television video signal, where M is the multiplicative product of an integer R times an integer Q, said integer R having a value near 16 and said integer Q having a value near 44, and clock signal generating means for generating 13.5 clock signals for clocking said digital transmission system whereby an even number N of said clock signals occurs during each interval of said M samples, where N is the multiplicative product of P times Q, P is a plural integer power of 2, and the difference D between P and R is a small integer.

20. A system according to Claim 19 wherein D
is unity.

21. A system according to claim 20 wherein P
equals 16 and R equals 17.

22. A system according to claim 19 wherein D
is five.

23. A system according to claim 22 wherein P
equals 16 and R equals 21.

24. A system as in claim 19 wherein the rate of said M samples is four times the rate of the color subcarrier of said standard television video signal.

25. A system according to claim 19 wherein M
is in the vicinity of 748.

-35- RCA 76, 709

26. A system as in claim 19 wherein said standard television video signal is a composite video signal.