FI68337B - ANORDING FROM THE DATA CODE - Google Patents

Description

ΓΒ1 KUULUTUSjULKAISU * ο τ τ η • θΓβ 8 ”OUTPUT G N GSSKRI FT Ο Ο Ο ζ) / C Patentti myönnetty 12 C8 1985 ^ Patent oath (51) Q4 / lnt.CI. * H ° 3 M 7 / 00 (21) Patent Tihakemus - Patent Application 783762 (22) Hakemispäivä - Application Date 07.12.78 (Fl) (23) Alkupäivä— Validity Date 07.12.78 (41) Tullut Christmas Kekseksi - Bllvlt ofTentllg 30.06.79

Patentti- ja rekisterihallitus Nähtäväkseen ja kuul.JulkH.un pvm.- 30.0 ^ .85

The Patent and Registration Board '' Application published and the extradition published (32) (33) (31) Pyydetty etuoikeus - Requested priority 2S. 1 2.77 Ruotsi-Sweden (SE) 7714926-8 (71) Oy LM Ericsson Ab, 02420 Jorvas, Suomi-Fin land (FI) (72) Magnus Bertil Ankarstrand, Jönköping, Ruotsi-Sweden (SE) (74) Oy Kolster Ab (54) Apparatus for AMI encoding of data signals - Laite tietosignalien AMI - koodaamiseks in the present invention relates to an apparatus for AMI (alternating mark inversion) encoding of data signals using a transversal filter.

As known, AMI coding is often used to reduce the necessary bandwidth when transmitting data signals. The AMI coding means that the zero bits in the information are transmitted as zero levels while the one bits are transmitted as alternating positive and negative pulses. Known AMI encoders utilize a bi-stable flip-flop that is reset after each 1-bit and acts as a memory to determine whether the next 1-bit should be rendered as a positive or a negative pulse.

In AMI transmission, the problem arises that a longer series of zeros results in loss of synchronization, so a re-encoding or "scrambling" of the transmitted data flow is necessary to break the monotonous zero level. This is accomplished according to the prior art with separate encoder before the AMI encoder.

68337 Prior to transmitting the data signals, a formation of the transmitted pulses is also required, which may conveniently be done by a transversal filter which, in order to filter the three-level signals, must contain at least two binary shift registers or an analog shift register.

A conventional switch for transmitting transcoded, AMI-encoded and filtered data signals must thus contain a separate encoder, an AMI encoder and a transversal filter. In the future, this device is called for simplicity AMI-S-F encoder.

The object of the invention is to provide a device for encoding and transmitting data signals which perform all three functions, thus "scrambling", AMT-coding and filtering, and which means a significant simplification and saving compared to previously known devices.

The basic idea of the invention is that in a binary shift register a flank-coded AMI code is formed, it is possible to perform all three of the above functions in the same device.

The device according to the invention is characterized as stated in the appended claims.

The invention is explained in more detail below with the aid of an embodiment example with reference to the accompanying drawing, in which fig.

Fig. 1 is a block diagram of a known AMI-S-F encoder; Fig. 2 is a schematic diagram of a device according to the invention and Fig. 3 is a schematic diagram showing how the transversal filter is constructed.

Figure 1 shows the principle of a conventional AMI-S-F encoder. The data flow is measured to a scrambler OM in order to break a potentially monotonous zero level occurrence. The re-encoded data signals are measured into an AMI encoder which converts the successive one-bits into alternating positive and negative pulses. The signals are then measured to a transverse filter TF to reshape them so that they obtain a shape suitable for transmission.

The invention provides a much simpler solution since these three functions are performed in a single circuit.

Fig. 2 is a schematic diagram of a device according to the invention. SK refers to a shift register whose 11 steps Q1-Q11 over each of whose impedances R1-R11 are connected to the plus or minus input of a differential amplifier in such a way that the difference signal from two adjacent steps at propagation of a change through the shift register makes a weighted contribution to the amplifier's sum signal as will be explained. In this case, the shift register is increased by the double data rate.

The data signals pass through a logic circuit L before they are measured at the input of the shift register SK. This logic circuit is constructed in such a way that the incoming data signal is measured to one of the two inputs of two NAND circuits 01 and 02, to the first over an inversion circuit IV1 and to the second directly. The second input to NAND circuits 01 and 02 is connected to Q1 and Q2, respectively, in the shift register, the first directly and the second over an inversion circuit IV1. By logic circuit L, it is established that the da byte is zero measured in the first stage Q1 in the shift register eats to this stage when the next clock pulse arrives and since the data bit is one it inverted in the second stage Q2 and measured in the first stage when the next clock pulse is coming.

The logic circuit L ensures that an incoming zero bit does not cause any change in the contents of the first shift register step, while an incoming one bit always causes a change regardless of whether the original content was one or a zero. In this way, a difference between the contents of the first and second stages will propagate throughout the shift register. This change can be sensed by the differential amplifier F in the form of voltage differences between the cell having the continuously output value corresponding to 0 and the cell whose contents are changed by receiving a 1-bit.

Fig. 3 shows in more detail the principle for the edge detection of an incoming 1-bit. Assuming that the content at a certain moment is equal in the first Q1 and in the second Q2 shift register step, no difference is obtained and the amplifier output signal becomes zero which corresponds to an input 0-bit. If the bed contains value 0 and Q1 is changed to 1 (positive edge), a voltage difference arises and at the amplifier's output a plus signal is obtained. Similarly, from the amplifier, a negative signal is obtained if the content of both cells is 1 and the content of Q1 is changed to 0 (negative flank).

If the 1-bit is propagated to the Q2 stage, the same signal still remains at the Q1 output and no output is obtained since only one flank can provide an output. In practice, the output signals from the shift register cells of a transverse filter are weighted to achieve a desired output signal form after summation. In the device of the invention, it is desired to provide an output signal corresponding to the characteristic of a conventional transversal filter. This can be accomplished as follows.

The differential amplifier connected to cells Q1, Q2 in the shift register with its resistance R1 gives the first coefficient 1 the transverse filter. The rest of the coefficient coefficients in the transversal filter are obtained by connecting new resistors to the differential amplifier in the same way, ie two resistors ^ R2 are connected to Q2 and Q3 respectively, giving the second coefficient. The third coefficient is obtained by connecting two resistors R3 to Q3 and Q4 respectively.

You can select a transversal filter with the following component values as an example.

Table 1 Step 12 3 6 789 Weighting of step +0.11 +0.17 -0.35 +0.22 +0.35 +0.32 -0.62 -1 -0.55 -0.15 output impedance 91k 59k 28.6k 1 + 5, ί + k 28.6k 31.2k 15.9k 10k 18.2k 67k 0m against this conventional transversal filter, where a propagated one is weighted with different values in different steps, the difference between two cells as the flank propagates to one of these, the closest transversal filter is formed as mentioned above. However, to achieve this, two impedances of each stage would be necessary.

To limit the number of impedances to only one of each stage, proceed as follows: In the new transverse filter with multiple inputs to the differential amplifier, the coefficient from the preceding step to the next step with the reverse sign is repeated, which means the formation of the difference between the output voltage from two successive steps. (flankavkänning).

Thus, the resulting coefficient in each step becomes the sum of the coefficient associated with that step and the coefficient from the preceding step with the inverse sign. The new coefficients are shown in Table 2.

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Table 2 68337 supplement +0.11 (+0.17 (-0.35) +0.22 (+0.35) +0.32 (-0.62 (-1 (-0.55) 0.15) before- "0.11)" Ο, Π) +0.35) "0.22) -0.35)" 0.32 +0.62) +100) +0.55 the steps +0.06 - 0.52 +0.57 +0.13 -0.03 -0.9¾ +0.38 + 0.1 + 5 + 0.1 + 0 +0.15 output signal output 91k 167k 19.2k 17 , 5k 77k 333k 10.6k 26.3k 22.2k 25k 66.7k signal + + - + + - - - + + + For example, as the table shows, the impedance for Q2 can be calculated as 0 ~, T6 = 167 k ohm

Threatened calculation has been performed for all steps.

Table 3 shows an example of the contents of the shift register and the corresponding output signal corresponding to a certain incoming data pattern. The left column contains the incoming data stream (one data pulse corresponds to two clock pulses), the other columns show the contents of the different shift register steps during each clock pulse, and the last three columns contain the signal polarities obtained at the differential amplifier inputs and its outputs.

6

Table11 3 68337

Data Contents of the shift register 12 3 4 5 6 7 ------ +

Ing. Ing. Ed.

0 0000000 000 0 0000000 000 1 1000000 + k1 0 + U1 1 1100000 0 + k2 + U2 0 1110000 000 0 1 1 1 1 0 0 0 0 0 0 1 0111100 -k1 0 -U1 1 0011110 0 -k2 -U2 1 1001111 + k1 0 + U1 1 1100111 0 + k2 + U2 1 0110011 -k1 0 -U1 1 0011001 0 -k2 -U2 As is the case, at the inputs of the differential amplifier the values with coefficients k1, k2 are weighted with plus-respect minus polarity. , so that at the amplifier output a voltage is obtained in accordance with the desired signal form.

Fig. 2 also shows a circuit which accomplishes the scrambling of the data signals before the broadcast. Three of the shift register steps, according to example Q12, Q14 and Q16, are connected to a logic circuit G2 which contains three exclusive or circuits. The steps Q12 and Q14 are connected to each input of the exclusive or circuit E01, while the step Q14 is also connected to one input of an exclusive or circuit E02 to whose other input the step Q16 is connected. The outputs of the exclusive or circuits E01 and E02 are connected to each input of an additional exclusive or circuit E03 from whose output the exclusive or sum of two consecutive bits in the AMI-encoded data stream is delayed by 6 7 data bits respectively. They are: to note that the flanks propagating through the shift register must be converted to 68337 pulses, which is why the flank must have reached the boundary between Q12 and Q13 in order for a pulse to rise at the E01 output of the circuit and the flange must have to the border between Q14 and Q15 in order for a pulse to occur at the output of the circuit E02.

The exclusive or circuit E03 output is connected to one input of an exclusive or circuit G1 to whose other input is measured the transmitted data signals and whose output data flow is measured to the logic circuit L. A 6 ~ 7 connection has been obtained. encoding according to the polynomial 1 + X + X which is usually called 127-bit scrambling.

As is the case, the invention has provided a device which simultaneously performs AMI coding, scrambling and filtering of an incoming data stream.

Claims (2)

8 Patent Claims: 68337 Device for AMI (alternating ground inversion) coding of data signals, characterized in that it contains a shift register (SK) whose steps over each impedance are connected to either of two inputs of a differential amplifier, a logic circuit (L) by which the data signals are fed to the shift register and to which the first two steps of the shift register are connected in such a way that if the binary value of the input signal is 0, the signal fed unchanged to the shift register and the input binary value of the shift register is input to the shift register. is propagated through the shift register, while upon receiving a signal with the binary value 1 a value opposite to the preceding value is input to the shift register and propagated through the shift register unchanged until the next 1 value is obtained, whereby the impedance values of the respective steps are dimensioned at in such a way that, when advancing a bit change through the shift register, the buckles are weighted difference differences are obtained from each step pair containing different bit values and the signal parts summed at the output of the differential amplifier during the change of propagation through the shift register form a signal corresponding to a desired signal characteristic, so that when changing the bits in the shift register from an 0 series a 1 series or vice versa a positive and negative output signal respectively is obtained, while in propagating an unchanged bit the difference between the output signal from two adjacent steps and consequently the output signal from the output of the differential amplifier becomes 0. 2. Device according to claim 1, characterized in that at least three of the steps of the shift register are connected to a logic circuit (G2) which, from the state in these steps, forms the exclusive or sum of two consecutive bits in the AMI-encoded data flow with a delay determined by the state of the step and has its output reconnected to one input of an exclusive or circuit (G1), the other input of which receives the data flow to be transmitted, so that to the input of the logic circuit is fed a decoded (scramble) data signal. Il