FI20105743A0 - Muistista lukeminen tai muistiin kirjoittaminen - Google Patents

Muistista lukeminen tai muistiin kirjoittaminen

Info

Publication number
FI20105743A0
FI20105743A0 FI20105743A FI20105743A FI20105743A0 FI 20105743 A0 FI20105743 A0 FI 20105743A0 FI 20105743 A FI20105743 A FI 20105743A FI 20105743 A FI20105743 A FI 20105743A FI 20105743 A0 FI20105743 A0 FI 20105743A0
Authority
FI
Finland
Prior art keywords
write
read
memory
Prior art date
Application number
FI20105743A
Other languages
English (en)
Swedish (sv)
Inventor
Szabolcs Szakacsits
Original Assignee
Tuxera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tuxera Inc filed Critical Tuxera Inc
Priority to FI20105743A priority Critical patent/FI20105743A0/fi
Publication of FI20105743A0 publication Critical patent/FI20105743A0/fi
Priority to PCT/FI2011/050597 priority patent/WO2012001234A1/en
Priority to JP2013517421A priority patent/JP6005637B2/ja
Priority to KR1020137002395A priority patent/KR101569372B1/ko
Priority to CN201180032435.9A priority patent/CN102971719B/zh
Priority to EP11736120.4A priority patent/EP2588964B1/en
Priority to US13/168,871 priority patent/US8775738B2/en
Priority to JP2016083229A priority patent/JP6145193B2/ja

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
FI20105743A 2010-06-29 2010-06-29 Muistista lukeminen tai muistiin kirjoittaminen FI20105743A0 (fi)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FI20105743A FI20105743A0 (fi) 2010-06-29 2010-06-29 Muistista lukeminen tai muistiin kirjoittaminen
PCT/FI2011/050597 WO2012001234A1 (en) 2010-06-29 2011-06-21 Reading or writing to memory
JP2013517421A JP6005637B2 (ja) 2010-06-29 2011-06-21 メモリへの読取り又は書込み
KR1020137002395A KR101569372B1 (ko) 2010-06-29 2011-06-21 메모리 읽기 및 쓰기
CN201180032435.9A CN102971719B (zh) 2010-06-29 2011-06-21 对存储器读取或写入的方法、设备及组件
EP11736120.4A EP2588964B1 (en) 2010-06-29 2011-06-21 Reading or writing to memory
US13/168,871 US8775738B2 (en) 2010-06-29 2011-06-24 Reading or writing to memory
JP2016083229A JP6145193B2 (ja) 2010-06-29 2016-04-18 メモリへの読取り又は書込み

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20105743A FI20105743A0 (fi) 2010-06-29 2010-06-29 Muistista lukeminen tai muistiin kirjoittaminen

Publications (1)

Publication Number Publication Date
FI20105743A0 true FI20105743A0 (fi) 2010-06-29

Family

ID=42308195

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20105743A FI20105743A0 (fi) 2010-06-29 2010-06-29 Muistista lukeminen tai muistiin kirjoittaminen

Country Status (6)

Country Link
US (1) US8775738B2 (fi)
EP (1) EP2588964B1 (fi)
JP (2) JP6005637B2 (fi)
KR (1) KR101569372B1 (fi)
FI (1) FI20105743A0 (fi)
WO (1) WO2012001234A1 (fi)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101873296B1 (ko) * 2011-09-15 2018-07-03 삼성전자주식회사 저장공간 확장이 가능한 단말기 및 그 저장공간 확장방법
US9921962B2 (en) * 2015-09-24 2018-03-20 Qualcomm Incorporated Maintaining cache coherency using conditional intervention among multiple master devices
KR20220022139A (ko) 2020-08-18 2022-02-25 에스케이하이닉스 주식회사 메모리 시스템, 메모리 컨트롤러 및 메모리 시스템의 동작 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0460730A (ja) * 1990-06-28 1992-02-26 Nec Corp キャッシュ制御方式
EP0667579A1 (en) * 1994-02-09 1995-08-16 Ballard Synergy Corporation Cache for optical storage device
JPH10269143A (ja) * 1997-03-25 1998-10-09 Mitsubishi Electric Corp ディスクキャッシュ装置のキャッシュパラメータ制御方法及びディスクキャッシュ装置
US6266742B1 (en) * 1997-10-27 2001-07-24 International Business Machines Corporation Algorithm for cache replacement
JPH11353230A (ja) * 1998-06-04 1999-12-24 Toshiba Corp コンピュータ装置
JP4508608B2 (ja) * 2003-11-13 2010-07-21 株式会社日立製作所 統合キャッシュを備えた記憶装置アダプタ
US7401188B2 (en) * 2005-06-29 2008-07-15 Intel Corporation Method, device, and system to avoid flushing the contents of a cache by not inserting data from large requests
WO2007072287A2 (en) * 2005-12-20 2007-06-28 Koninklijke Philips Electronics N.V. Method of controlling disk accesses between a hard-disk drive and a number of stream buffers
US7409502B2 (en) 2006-05-11 2008-08-05 Freescale Semiconductor, Inc. Selective cache line allocation instruction execution and circuitry
WO2008004149A2 (en) 2006-06-30 2008-01-10 Nxp B.V. Flash memory device having a flash cache portion and a method for using the same
US20080184003A1 (en) * 2007-01-30 2008-07-31 Kabushiki Kaisha Toshiba Data transmission control apparatus and data transmission control method
US7895397B2 (en) * 2007-09-12 2011-02-22 Intel Corporation Using inter-arrival times of data requests to cache data in a computing environment
US7886110B2 (en) * 2007-12-27 2011-02-08 Intel Corporation Dynamically adjusting cache policy based on device load in a mass storage system
US8914579B2 (en) * 2008-02-29 2014-12-16 Panasonic Corporation Access device, information recording device, controller, and information recording system
US8433854B2 (en) * 2008-06-25 2013-04-30 Intel Corporation Apparatus and method for cache utilization
US8601213B2 (en) 2008-11-03 2013-12-03 Teradata Us, Inc. System, method, and computer-readable medium for spool cache management

Also Published As

Publication number Publication date
CN102971719A (zh) 2013-03-13
JP6145193B2 (ja) 2017-06-07
EP2588964A1 (en) 2013-05-08
KR101569372B1 (ko) 2015-11-16
JP2016149155A (ja) 2016-08-18
KR20140012934A (ko) 2014-02-04
EP2588964B1 (en) 2019-12-25
US8775738B2 (en) 2014-07-08
WO2012001234A1 (en) 2012-01-05
JP2013533551A (ja) 2013-08-22
JP6005637B2 (ja) 2016-10-12
US20110320718A1 (en) 2011-12-29

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Legal Events

Date Code Title Description
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