FI20060697A0 - Procedure for manufacturing conductors and semiconductors - Google Patents

Procedure for manufacturing conductors and semiconductors

Info

Publication number
FI20060697A0
FI20060697A0 FI20060697A FI20060697A FI20060697A0 FI 20060697 A0 FI20060697 A0 FI 20060697A0 FI 20060697 A FI20060697 A FI 20060697A FI 20060697 A FI20060697 A FI 20060697A FI 20060697 A0 FI20060697 A0 FI 20060697A0
Authority
FI
Finland
Prior art keywords
semiconductors
procedure
manufacturing conductors
conductors
manufacturing
Prior art date
Application number
FI20060697A
Other languages
Finnish (fi)
Swedish (sv)
Other versions
FI20060697A (en
FI121562B (en
Inventor
Heikki Seppae
Mark Allen
Original Assignee
Valtion Teknillinen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valtion Teknillinen filed Critical Valtion Teknillinen
Priority to FI20060697A priority Critical patent/FI121562B/en
Publication of FI20060697A0 publication Critical patent/FI20060697A0/en
Publication of FI20060697A publication Critical patent/FI20060697A/en
Application granted granted Critical
Publication of FI121562B publication Critical patent/FI121562B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Powder Metallurgy (AREA)
FI20060697A 2006-07-21 2006-07-21 Method for the manufacture of conductors and semiconductors FI121562B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FI20060697A FI121562B (en) 2006-07-21 2006-07-21 Method for the manufacture of conductors and semiconductors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20060697A FI121562B (en) 2006-07-21 2006-07-21 Method for the manufacture of conductors and semiconductors
FI20060697 2006-07-21

Publications (3)

Publication Number Publication Date
FI20060697A0 true FI20060697A0 (en) 2006-07-21
FI20060697A FI20060697A (en) 2008-01-22
FI121562B FI121562B (en) 2010-12-31

Family

ID=36758304

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20060697A FI121562B (en) 2006-07-21 2006-07-21 Method for the manufacture of conductors and semiconductors

Country Status (1)

Country Link
FI (1) FI121562B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI122011B (en) 2007-06-08 2011-07-15 Teknologian Tutkimuskeskus Vtt Method for Producing an Electronic Module, Intermediate to Produce an Electronic Module, Memory Element, Printed Electronic Product, Sensor Device, and RFID Tag
FI122014B (en) 2007-06-08 2011-07-15 Teknologian Tutkimuskeskus Vtt Method and apparatus for the functionalization of nanoparticle systems
FI122644B (en) 2007-06-08 2012-04-30 Teknologian Tutkimuskeskus Vtt Process for forming electrically conductive or semiconducting paths on a substrate and using the method for producing transistors and producing sensors

Also Published As

Publication number Publication date
FI20060697A (en) 2008-01-22
FI121562B (en) 2010-12-31

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Legal Events

Date Code Title Description
MM Patent lapsed