FI20050388A0 - Circuit and method for quickly and efficiently calculating the sum of the absolute values of differences - Google Patents
Circuit and method for quickly and efficiently calculating the sum of the absolute values of differencesInfo
- Publication number
- FI20050388A0 FI20050388A0 FI20050388A FI20050388A FI20050388A0 FI 20050388 A0 FI20050388 A0 FI 20050388A0 FI 20050388 A FI20050388 A FI 20050388A FI 20050388 A FI20050388 A FI 20050388A FI 20050388 A0 FI20050388 A0 FI 20050388A0
- Authority
- FI
- Finland
- Prior art keywords
- differences
- sum
- quickly
- circuit
- absolute values
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/20—Analysis of motion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/544—Indexing scheme relating to group G06F7/544
- G06F2207/5442—Absolute difference
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20050388A FI117956B (en) | 2005-04-15 | 2005-04-15 | Circuit and method for calculating a sum of absolute differences quickly and efficiently |
PCT/FI2006/000117 WO2006108912A1 (en) | 2005-04-15 | 2006-04-13 | Circuit and method for computing a sum of absolute differences fast and effectively |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20050388 | 2005-04-15 | ||
FI20050388A FI117956B (en) | 2005-04-15 | 2005-04-15 | Circuit and method for calculating a sum of absolute differences quickly and efficiently |
Publications (3)
Publication Number | Publication Date |
---|---|
FI20050388A0 true FI20050388A0 (en) | 2005-04-15 |
FI20050388A FI20050388A (en) | 2006-10-16 |
FI117956B FI117956B (en) | 2007-04-30 |
Family
ID=34508086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20050388A FI117956B (en) | 2005-04-15 | 2005-04-15 | Circuit and method for calculating a sum of absolute differences quickly and efficiently |
Country Status (2)
Country | Link |
---|---|
FI (1) | FI117956B (en) |
WO (1) | WO2006108912A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9658829B2 (en) | 2009-10-19 | 2017-05-23 | Intel Corporation | Near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864372A (en) * | 1996-12-10 | 1999-01-26 | United Microelectronics Corporation | Apparatus for implementing a block matching algorithm for motion estimation in video image processing |
US5838392A (en) * | 1998-03-19 | 1998-11-17 | United Microelectronics Corp. | Adaptive block-matching motion estimator with a compression array for use in a video coding system |
FI110909B (en) * | 2001-09-06 | 2003-04-15 | Nokia Corp | Method for performing motion estimation at video coding, video coding system and video coding device |
FI110744B (en) * | 2001-09-06 | 2003-03-14 | Nokia Corp | Method of Performing Motion Estimation in Video Coding, Video Coding System and Video Coding Device |
-
2005
- 2005-04-15 FI FI20050388A patent/FI117956B/en not_active IP Right Cessation
-
2006
- 2006-04-13 WO PCT/FI2006/000117 patent/WO2006108912A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2006108912A1 (en) | 2006-10-19 |
FI20050388A (en) | 2006-10-16 |
FI117956B (en) | 2007-04-30 |
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Legal Events
Date | Code | Title | Description |
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FG | Patent granted |
Ref document number: 117956 Country of ref document: FI |
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MM | Patent lapsed |