FI117956B - Circuit and method for calculating a sum of absolute differences quickly and efficiently - Google Patents

Description

117956

Circuit and Method to Calculate Sum of Differences Absolute Values Quickly and Effectively - Krets och method för att räkna en sum av absoluta skiiinader snabbt och effektivt

TECHNICAL FIELD

The invention relates to the field of digital video coding. In particular, the invention relates to determining a motion vector to determine how much and in what direction a macroblock of a digital video frame has moved relative to the corresponding macroblock of the reference frame.

BACKGROUND OF THE INVENTION '

Motion estimation is one known method of reducing the time redundancy between consecutive video frames, and is commonly used in digital video encoding methods. The frame of the digital video stream is divided into non-overlapping blocks, commonly referred to as macroblocks. For each macroblock, ΜΙ 5 pits to find the previous macroblock that most closely matches the reference frame, i.e.. a frame of reference to find a macroblock that is as similar in pixel content as possible to the current macroblock. As part of the encoding of the current frame, a motion vector is formed which indicates how much • ♦ v .; and in which direction the current macroblock has moved best from the corresponding one; 20 large macroblocks. In addition, a difference signal is needed to indicate how much and in what way the current macroblock differs even from the best corresponding prior; ***: macroblock.

··· • · ♦ · · · The overall size of a macroblock is 16 times 16 pixels. Strictly speaking, the generic definition of a macroblock * · * ··· 'means a 16x16 luminance block and two open space 8x8 chrominance blocks, but since the luminance and chrominance components are highly correlated, it is common to treat: ***: luminans only .

• · ·

Motion estimation is by far the most costly part of digital video coding because of its high computational need and because of the: -. *. Components performing 30 computations require relatively large microchip space.

The inexpensive motion estimation architecture is one that can be implemented with as few computation operations and logical gates as possible. Compromises may be needed, with a certain increase in microchips! -; i 2 117956 may be acceptable if a significant improvement in computing speed is achieved, and vice versa.

Figure 1 shows a generally accepted solution, the so-called three-stage solution. pipeline, which is a general arrangement for defining what is known as the current macro block and candidate macro block. SAD (sum of the absolute values of the differences).

SAD measures how closely the candidate macroblock matches the current macroblock, i.e.. whether the candidate macroblock could best fit into the corresponding prior macroblock. The first degree consists of a set of difference value units 101. The current macroblock and the candidate macroblock read a number of pixels, and spatially corresponding pixel values are fed in pairs to the difference value units. As the name suggests, each difference value unit 101 calculates the absolute value of the difference between the two pixel values it receives. The summation of these is performed in a second order, commonly referred to as a compression structure 102. It calculates the sum of the absolute values of all differences it receives from the first order and sends the result to the third order as a minimum SAD determiner 103. When comparing a current macroblock which led to the lowest SAD value, i.e. which was most similar to the current macroblock.

Motion estimators based on the general solution of Figure 1 are known from, for example, prior art US 5,864,372 and US 5,838,392. Let's look at some of their features in more detail.

• ♦ • · · · · ·

Figure 2 shows the so-called Ohen difference value unit used here as an example of the * · \ .Γ known difference value unit 101. It adds the operand A (which in this example is an eight-bit value a7, a6 ..... a0) and the operand B (here; * · * 25 b7, b6, ..., bo) The complementation of two complementaries of B is accomplished bitwise by inverting B and bringing the default value '1' to the memory number range of adder 201. If operand A is initially larger , the adder directly generates the correct ϊ. · |: positive result and indicates the memory number shift (c7 = T) that is inverted: C = 0. If the operand B was originally larger, the adder 201 gives a double complement of 30, which is converted to a positive line. XOR output ports * ··· [202 which this time get their second input c7 = C = 1. The C value also includes a correction bit which is passed to the next step of the SAD specification: to be taken into account there. in notation 'ABS reminds you that • · · ·: ***: correction bit C is missing from the result.

• · · 3 117956

Figure 3 shows an adder tree known from the scientific publication Q. Shu and H. Chen, "An Efficient Implementation of Motion Estimation Algorithms," in Proc. 4th Int. Conf. Solid-State and Integrated Circuit Technology, Oct. 1995, p. 697-699. The adder tree was, in fact, only a precursor to the actual compression structures-5, but it provides a very intuitive way of understanding the purpose of the secondary order shown in Figure 1. The absolute values of the pixel differences between the current macroblock and the candidate macroblock are fed in pairs to the first row adder 301 and the third row adder 303 to the output adder 304. Each of the adder 301, 302, 303 and 304 10 also receives the selected correction. The sum tree output consists of the final sum 'SAD0..15 and the remaining correction bit C15.

Figure 4 illustrates a compression structure known from US 5,864,372, here in a simplified version that receives as input only four difference it-15 standing values 'ABS0 to' ABS3 and the corresponding correction bits CO-C3. Compression structure 401 includes a plurality of cascaded 4: 2 compression unit pairs, one of which is seen at partial magnification 402, Going toward the most significant bits comes after which the compression unit pairs are somewhat replaced by simpler circuits. Each of said cascaded 4: 2 20 compression unit pairs and said simpler circuits forms one bit in the SAD S vector, which is a sum vector, and one bit in the SAD_C vector, which is a memory number vector. The sum vector SAD_S and memory - [; *; * the number vector SAD_C are temporarily stored in the output registers 404 and 403 and: *. ** is fed back as additional information to the compression structure 401.

Figure 5 shows the minimum SAD descriptor proposed in US 5,838,392. One feature of this solution is that it never actually calculates the actual SAD. values, but only handles sum vectors (SAD_S vectors, paths) and memory number vectors (SAD_C vectors) separately, the minimum values of which are · · · stored in summary register 501 and memory number register 502. 4: 2 • # * ·; · * 30 compression units and the combination of adder 504 performs two complement subtraction between the current and minimum SAD, whereby the memory bit obtained at the output of adder 504 ·: ··· indicates the sign of the result of the subtraction. “J / of adder 504 is '0 'at the time of comparison, the current SAD value is smaller than the time before ... · 35 emmin stored minimum SAD, so current SAD stores The inverter 505 and the two logic ports 506 and 507 properly control the 4 117956 storage process. In addition, motion vector input data (represented by (k, I) in Figure 5) is stored in register 508. A memory bit value of '1' at the reference instant indicates that the current SAD has exceeded the minimum SAD. An "end_tag" statement is available to indicate such a situation and can be used, for example, to terminate the SAD calculation prematurely.

The disadvantages of the known solutions include: excessive use of integrated circuit mode, counting delays, and sub-optimal overall performance.

It is an object of the present invention to provide a circuit and method for calculating the SAD and finding the minimum SAD with the best performance and area efficiency.

The object of the invention is achieved by a structure in which the correction bits are subjected to special processing quite early in the computation process, most preferably already from the difference values units, and only combined with the processing of the absolute values of the differences in the compression step.

The circuit of the invention is characterized by what is disclosed in the characterizing part of the independent claim on the circuit.

The method according to the invention is characterized by what is stated in the characterizing part of the independent claim to the method.

* · * · · *** *. ·. · *. Further, the invention relates to a digital video encoder characterized by the features of the independent claim of a digital video encoding device.

• · • · ···

A first aspect of the invention is an advanced difference value unit employing: ***; one of the operands is a one-complement representation, not a two-complement representation, as was usual in previous solutions. In the unit of difference. . ·. 25 generates a memory number bit, which is used bitwise inverter as needed. **. to work, but a low-performance "end-around" memory chain and ♦ · no need for continuous T-memory input. The memory number bit also forms a correction bit. * "*: Correction bits formed in two adjacent difference value units can already be combined in a half-adder or similar circuit unit: * ·. 30 before being exported to the second stage of the three-stage pipeline process.

• ♦ · * ·· · · · ·

Another aspect of the invention is a second degree, i. a compression structure where the correction bits are initially processed from a 5 117956 main compression tree used to process uncorrected difference values in a separate repair tree. A preferred configuration of the compression structure is based on the use of CSAs (carry save adder) which can be allocated and connected in different ways. In a preferred embodiment, the CSA adder is used at six levels of the main compression tree and three 5 levels of the repair tree, whereby compressed correction information is applied from the second and third levels of the repair tree to the respective inputs of the third, fourth, fifth, and sixth level CSA The strategy of combining the compressed correction data with the main compression tree is most preferably formulated so that the final sum and memory number vectors obtained from the compression structure have as few common bit positions as possible.

The third aspect of the invention is a third step, i.e.. a minimum SAD assay unit that can optionally implement various early termination mechanisms. These include e.g. comparing the current SAD value with the previous minimum SAD-15 value during the computation while the current SAD is still being computed, when exceeding the previous minimum completes the computation before it is completed. In addition, a negative downward bonus may be added to the value of the first non-motion SAD, making it statistically more likely that no motion vector will be transmitted at all. As a third mechanism affecting the operation of the minimum SAD assay unit, the concept of thresholds is introduced. Can be set. one or more thresholds for the SAD calculation such that whenever the current calculated SAD exceeds the threshold, a certain threshold-related decision is made to continue the current SAD calculation. Unlike the first mechanism, the ίV threshold is a parameter value and not the result of any previous SAD calculation.

·· ♦ • t * * • · ·:. ·. The exemplary embodiments of this application are not to be construed as limiting the applicability of the appended claims. The term "comprising" is used in this patent application as an open limitation which, however, does not exclude features not mentioned herein. The features mentioned in the dependent claims are free to be combined unless specifically stated otherwise.

* ♦ · • · • · ** '. The novel features considered to be characteristic of the invention are set forth in detail in the appended claims. However, the invention itself, its structure and operating principle, and further objects and advantages thereof, are described below: ***: by means of some embodiments and with reference to the accompanying drawings.

* * *.

6 117956

Figure 1 shows a known principle of three steps of SAD calculation, Figure 2 shows a known Chen difference unit, Figure 3 a conventional summation tree, Figure 4 a known concept of compression structure, Figure 5 illustrates a known Chen minimum SAD determination unit, Figure 6 illustrates an embodiment of the invention SAD calculation circuit and method.

Fig. 7 shows a part of a difference value unit according to an embodiment of the invention; 10 Fig. 8 shows a part of a compression structure according to an embodiment of the invention; Fig. 9 shows another part of a compression structure according to an embodiment; Fig. 11 shows a mini-mi-SAD detector according to a simple embodiment of the invention; Fig. 12 shows a minimum-SAD detector according to a more versatile embodiment of the invention; Fig. 13 shows a SAD according to Fig. 6 adapted to the embodiments shown in Figs. 14 and 14 illustrate a delay and area comparison of different SAD calculations and a video encoder according to an embodiment of the present invention.

• · «« * • · · • · ·

Figure 6 is a schematic representation showing motion estimation circuitry and method implementing SAD for use as part of digital video encoding. Consistently with the previous designations, it is assumed that there is a current macroblock for which a motion estimate should be formed, as well as a number of candidate macroblock blocks from which the most appropriate one should be identified, i. basically the one that least differs •. from the current macroblock. The pure application of this basic criterion can • • ·. · * ·. There is a slight deviation, for example, by using a "zero bonus" which favors one of the candidate macroblock blocks, but these details will be discussed below.

• · • ♦

• M

·: ··: The first degree 601 consists of difference units 602, each of which is a sequence. *, used to determine the absolute value of the difference between two multi-bit input values. The difference * * · stability units 602 are equal to the number of pixels that can be simultaneously compared between the current macroblock and the candidate-35 macroblock. In Figure 6, it is a general assumption that the macroblocks being compared are 16x16 pixels in size and that 7,117,956 one row (or column) of pixels from each macroblock are compared at a time. Thus, there are sixteen difference value units 602, of which only four are shown separately in the figure. It is also assumed that the pixel values are represented by eight bits, whereby each of the difference value units 602 receives two eight-bit input values and 5 generates an eight-bit uncorrected output value and a memory bit.

It would be very easy to change the number of difference value units and / or bit inputs in each difference value unit if other design permission parameters were used, or to select the pixels to be compared according to a selection strategy other than simply row or column at a time.

10 The second stage 611 is a compression structure that receives the uncorrected output values and the correction bits (or more generally "correction values" or only "corrections") from the differential equation units 602 of the first order 601.

II

in the compression structure, the second stage includes a main compression tree 612 and a separate repair tree 613. The former is arranged to receive the uncorrected difference values and the second order previously compressed sum and memory number vectors as feedback. The repair tree is arranged to receive repairs. Compressing the correction bits in the correction tree 613 generates a plurality of compressed correction values that are input at appropriate positions in the main compression tree 612.

As a result, the second stage 611 generates sum and memory number vectors which together express the sum of the absolute values of the differences in the pixel row (or array or group) that were simultaneously compared. These are exported to third degree # #. · *. · * Tea stage 621, which consists of a minimum SAD descriptor. It cumulates line item-: * · *; full (or column specific or group specific) SAD values, compare cumulative · '**; sum to the minimum value at a convenient moment and generate output values with · ···:. ·. 25 sa is the minimum SAD found. Third stage 621 also receives some control input. * ··! and generates some other outputs which may be used, for example, to implement the mechanisms of premature termination of the earth controlled by a separate control member (not shown in Figure 6).

• · ϊ • * ·

Figure 7 shows a preferred arrangement of two adjacent first order · * ·. Of the 30-handed difference value units 602, the difference values shown in the figure * · form absolute values of the differences between the 0 and the 1 pixel pair. The basic design of each differential cavity unit 602 is similar to the known Chen solution (see Figure 2), but with significant differences in detail. In the figure to the right, the difference value unit has an 8-bit adder 711 that processes operand A 35 (a7 ... a0) and inverted operand B (b7 ... bo, shown before bit inverting). Instead of two complement representations, the 8-byte bit adder 711 uses 8 117956 for operand B to add a single complement representation, i.e.. S = A + B. If operand A was smaller (or equal) than operand B, the resulting negative result S (S7 ... S0) is bit-inverted at XOR gates 712 to obtain the correct positive value, and no additional correction bit is needed (C7 = Ό '). However, if operand A was greater than 5 than operand B, the 8-bit adder 711 would produce the correct positive result S minus one. Since the required "end-around" number insertion does not change the outgoing memory number information (C7), an immediate "end-around" number insertion is unnecessary in this case. Thus, the memory number bit (C7 = '1') formed by adder 711 is forwarded as a correction bit and a one-bit error correction is performed 10 later.

The formulas describing the operation of the differential value units 602 are as follows:

, ABs-iA + ^ = A + (28-1 "B) s (AB ~ 1) mod (28) jaC = 1, A> B [A + B = 28-1 ~ {a + (28-1- B)) = BA and C = 0, A <B

Thus, the memory number input of the adder can be completely eliminated without any hardware cost. This is a significant difference to Chen's method, which required continuous input of '1' memory numbers.

Another difference from all known methods is that the difference value unit 602 allows for the immediate accumulation of correction bits without any additional delay-: Y. Note that the left-hand difference unit is exactly the same as described above; the memory bit output is only drawn on the opposite side of the 8-bit * · adder 701 for easier illustration! ···. the principle of immediate correction bit accumulation. The correction bit of the left-hand 8-bit * * adder 701 and the right-hand bit of the 8-bit adder 711 are inverted, without inversion, as inputs CO and C1 to the half-adder 721, which converts * ··· * 25 to the two-bit correction bit vector C0..1 . When all the difference value units in the 16-channel primary stage are respectively paired, the first-order output consists of sixteen 8-bit uncorrected difference-state * ... · vectors'ABS0, 'ABS1, ...,' ABS15 and eight 2-bit correction bit vectors . ···. C0..1, C2..3, ..., C14..15. Using half-sumers to form correction bit vectors erases information about the exact value of each individual correction bit, but this does not adversely affect further processing; on the contrary, generated 2-bit correction vectors are better suited for use in the compression according to an embodiment of the invention. .

. 9 117956

Figures 8 and 9 show preferred embodiments of the main compression and repair wood. The main compression tree of Figure 8 receives new input data ('ABSO,' ABS1, ..., 'ABS 15; C0..1) from first order difference value units and feedback data (SAD_S (pre), SAD_C (pre)) from its own output registers (not shown 5). the figure). In addition, there is an INIT input to reset the feedback values at the beginning of a new SAD calculation. The feedback sum vector SAD_S (pre) has 16 bits which, after the port line that allows formatting, are denoted ssis, ssi4, ..., sso, or briefly just SS15..0- For reasons discussed later, the feedback memory vector SAD_C (pre) has three bits less , ie. only 13 bits, 10 respectively after the initialization ports SC15, sci4, ..., sc3 or SC15..3. Note that all sub-index numbers, such as "SC15..3". refer to the corresponding bit positions. In all cases where an entry refers to multiple bit positions, these are given in the subscript from the most significant to the least significant bit position. Normal-sized numbers in the correction bit vector-15 entries, such as CO..1 or C12..13, refer only to those differential value units from which the correction bits were included in the half-adder that formed that correction bit vector.

In Figure 8, the input and output bit widths of the CSA adder are denoted by the MSB ... LSB (most significant bit ... least significant bit) principle. In all CSA-20 adderers, the left output generates partial memory numbers and. . the right output represents a partial sum. Most CSA summer • ♦ · ***; 's have three inputs except for one dual-input CSA sumer in the correction * · 1 ·· tree. The CSA adder 801, 802, 803, and 804 having an exceptional input ·· ♦: V width are marked with an asterisk and their structure is explained by the usual CSA sum · · · · ... ... ϊ 25 in Figures 10a. , 10b, 10c and 10d. In these marked CSA adder, the input bit stages that receive bits from all three inputs are implemented by size aggregators, while the bit stages which have only ··· two inputs are implemented by the semi-adder. Unmarked three-input CSA-. the adder is completely implemented by size adder.

* The top level of the main compression tree has six CSA admitters with the following inputs and outputs: 4 4 4 4 4 4 4 1 1 1 1 1 1 1 ·••••• ««

Table 1: CSAs numbered from left to right 10 117956 _Leather Input Middle Input Right Output Right Output CSA 1 'bits 7..0:' bits 7..3: 'bits 7..0:' bits 8..1 ' bits 7..0

SS7..0 SC7..3 'ABSO

* bit 2: constant '0 '' bits 1..0: __C0..1 _______ CSA 2 'bits 7..0:' bits 7..0: 'bits 7..0:' bits 8..1 'bits 7..0 'ABS1' ABS2 'AB S 3___ CSA 3' bits 7..0: 'bits 7..0:' bits 7..0: 'bits 8..1' bits 7..0 _'ABS4 'ABS5' ABS6___ CSA 4 'bits 7..0:' bits 7..0: 'bits 7..0:' bits 8..1 'bits 7..0 _'AB S 7' ABS8 'ABS9___ CSA 5 'bits 7..0:' bits 7..0: 'bits 7..0:' bits 8..1 'bits 7..0 _'ABS 10' ABS 11 'ABS 12___ CSA 6' bits 7.. 0: 'bits 7..0:' bits 7..0: 'bits 8..1' bits 7..0 _ ['ABS13' ABS14 | 'ABS15 __ The second top level of the main compression tree has four CSA adder the following inputs and outputs: .. 5 Table 2: CSAs numbered from left to right • »» ♦ · ♦ * · _ _____: V: _Leather Input Middle Input Right Output Right Output CSA 1 'bits 8..1:' bits 8..1: 'bits 8..1:' bits 9..2 'bits 8..1 top top level top level level ** ·· * CSAV.nva- CSA2: va- CSA 3 va- * · _ output its output its output _____ C '.: CSA 2' bits 7..0: 'bits 7..0:' bits 7..0: 'bits 8..1' bits 7..0 max. top level top level level. CSAI.noi- CSA2: noi- CSA3: no ;;; * kea output kea output kea output ___ ** ·: ·: CSA 3 'bits 8..1:' bits 8..1: 'bits 8..1 : 'bits 9..2' bits 8..1: ** ·. top folder m. top level top level level CSA4: va- CSA5: va- CSA6 - output its output its output ____? CSA 4 'bits 7..0:' bits 7..0: 'bits 7..0:' bits 8..1 'bits 7..0 ·· *. top folder m. top level top level level CSA4: no- CSA 5 o- CSA 6 very good output good output good output _____ 11 117956 The third level of the main compression tree has three CSA adders with the following inputs and outputs:

Table 3: CSAs numbered from left to right _ Left Input Middle Input Right Output Right Output CSA1 * bits 9..2: * bits 3..2: 'bits 9..2:' bits 10..3 'bits 9. .2 second level outputs A and B of the second level CSA 1 correction tree CSA 3 _leaf output__leaf output__CSA 2 'bits 8..1:' bits 8..1: action 'bits 8.1:' bits 9..2 'bits 8..1 second level second level second level CSA 1 right CSA 2 right CSA 3 right output its output right output ___' CSA 3 'to bit 8' bits 8..1 : act 'bit 8: sc8' bits 9..1 'bits 8..0' bits 7..0 level 'bits 7..0: second level CSA 4 second level CSA 2 second output CSA 4 right output 'bit 0: output k output C correction __ tree ____] ___ 5 The fourth level of the main compression tree has two CSA adders with the following inputs and outputs: * · ***** Table 4: CSAs numbered from left to right »·« * * · 4 · «r ____ ^ ^ _Light Input Middle Input Right Input Left output True output; ... * 'CSA 1' bits 10..3: 'bit 10:' bit 10; 'Bits 11..3' bits 10..2 third ssio scio: level CSA 'bits 9..2:' bits 9..2: »« · ·. ·· *. 1 left third third

entry level CSA level CSA

'Bit 2: output 1 right 2 left J # ·': D correction output output ** ·. tree _____; __ / CSA 2 'bit 9: ssg' bits 9..1: 'bit 9: sc9' bits 10..2 'bits 9..1 • **:' bits 8..1: third 'bits 8 ..1: • · · Third Level CSA Third * ·

. Level CSA 3 Left Level CSA

: 2 right output 3 right ·· «·. * ··. output at output 7 ____ MSB __ 12 117956 The fifth level of the main compression tree has one CSA with the following inputs and outputs:

Table 5: _Light Input Middle Input Right Input Left Output Right Output CSA 'bit 11:' bit 11: 'bits 9..1:' bits 12..2 'bits 11..1 its fourth

'Bits 10..2:' bits 10..2: level CSA

fourth fourth 2 right level CSA level CSA output 1 right 2 left output output 'bit 1: output' bit 1: output E correction F from correction tree_wood_____ 5 The sixth level of the main compression tree has two CSA adders having the following inputs and outputs:

Table 6: CSAs numbered from left to right _ Left Input Middle Input Right Output Right Output CSA 1 'bits 15..12:' bit 12: bits 15..12: 'bits 15..13' bits 15. .12 • · ♦ • · SS15..12 dennen ta- SC15..12: son CSA ··· left.

I output MSB___ _ CSA 2 'bits 11..3:' bits 11..2: 'bits 11..2:' bits 12..3 'bits 11..2 ·· ♦ Fourth Pt. level five. level. level CSA: correct CSA * · '··. ···. CSAI.nva- nothing. near output it output 10 10MSB 'bit 2: output LSB G correction:! ·. of the tree • aa - · - - - - - • a a «• a a aa a a *** There are two CSA sumers at the top level of the repair tree with the following inputs and 10 outputs:

Table 7: CSAs numbered from left to right 13 117956 _Leather Input Middle Input Right Output Right Output CSA 1 'bits 1..0:' bits 1..0: 'bits 1..0:' bits 2..1 ' bits 1..0 C2..3 C4..5 C6..7 ___ CSA 2 'bits 1..0:' bits 1..0: 'bits 1..0:' bit 2 'bits 1..0 C8 ..9 C10..11 C12..13 'bit 1: ____ output E__'

At the second level of the repair tree, there are two CSA adders with the following inputs and outputs: 5 Table 8: CSAs numbered from left to right _Leather Input Middle Input Right Output Right Output CSA 1 'bit 2: -' bit 2: 'bit 3: 'bit 2:

top folder m. top level level output A output B

CSA 1 or CSA 2 left. closer. output MSB__ don MSB _________-CSA 2 'bits 1..0:' bits 1 ..0: 'bits 1 ..0:' bit 2: 'bit 1 max. top level output D 'bit 0 of level C14..15:

CSA1: oA bit 1 of CSA 2 output C

• · · *. · .__ kea output kea output

• · · 11> I | I I

• * • φ · • t ·

• I

. ···. In the third level of the repair tree, there is one CSA adder with the following inputs and! **: 'j outputs: · 9 Ta 9 9 9 9 9 Table 9:,. Right Input Left Output Right Output Ϊ · '.' CSA 'bit 1:' bit 1: act 'bit 1: act' bit 2: 'bit 1:

*: ** top level its level its level output G output F

CSA1: nva- CSA2: nva- CSA 2 oi- * "*: nothing closer. Outgoing output

• __d LSB dön LSB MSB

• · · “io • · *** During operation, the sum and memory bit bits formed by the three-stage repair tree of Figure 9 are exported one by one to the master command of Figure 8. 14 117956 for pressed wood suitable for otherwise unused CSA inputs. Bold pairs of letters A through G refer to the relationships between repair tree outputs and main compression tree inputs. In addition, Figure 8 shows in bold the numbers of bit stages that receive bits from the correction tree. The LSBs SS7..0 and SC7..3 of the conditionally initialized previous sum-5 and memory number vectors are passed to the first stage of the main compression tree as shown in Figure 8 and Table 1. A plurality of intermediate bits from these vectors, namely ssn..8 and SC-11..8, are applied separately to the main compression tree.

In Figure 8, these intermediate fittings are marked with the corresponding inserts. by circles (sum vector bits) and squares (memory number vector bits) around bit rate numbers. The MSBs of these 10 vectors, ssis, .i2, and SC15..12, are accumulated in the final stage of the main compression tree.

The compressed memory number vector SAD_C (cur) has 13 bits, with the 3 most n significant bits (MSB) coming from the left output of the sixth level CSA 1.

The rest of those bits come from the left output of the sixth level CSA 2.

15 The compressed sum vector SAD_S (cur) has 16 bits with 4 MSBs coming from the right output of the sixth level CSA 2, the next 10 bits coming from the right output of the sixth level CSA 2, the next bit (bit stage 1) is The least significant bit (LSB) and the last bit (bit rate 0) of the CSA right output is the LSB of the third level CSA 3 right output.

8 and 9 have the advantageous feature of reducing the number of operands at the earliest possible stage. Although: Y: the earliest possible operand subtraction somewhat increases the area requirement: * · *, · in the circuit implementation, it also reduces to the sum of the compressed sum vectors. (SAD_S (cur)) and memory bit vectors (SAD_C (cur)) are common bit rates:!, 25 den. In this context, a common bit rate is a bit degree that • · · ”.Y does not exist in only one of the vectors mentioned. Without the introduction of the correction bits, the main compression tree would be able to reduce the number of common bit stages from 16 to 12. Thanks to the separate structures developed to accumulate the correction bits, the compression tree structure of Figures 8 and 9 can reduce the number of common bit stages From 16 to 13, which is only one bit order less than the theoretical maximum; common bit steps are ssi5..3 and scis, .3 Reducing the number of common bit * * · paths does not necessarily increase the execution speed of the final sum and memory vectors, because the fast adder delay is not: typically not a steadily increasing function of the adder bit width.

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However, the number of common bit stages reduces hardware costs due to the narrower implementation of the adder and the smaller number of registers in the later stages of the motion estimator.

The first correction bit vector C0..1 can be immediately exported to one of the zero-order CSA summers in the main compression tree because the three least significant bits of the previous SAD 5 compressed memory number vector are idle as described above. Looking at a prior art compression structure such as that shown in Figure 4, where all 16 correction bits are applied to the O-bit rate of the CSA inputs, it can be seen that this prior art solution causes - as compared to a traditional CSA tree with no 10 bit enhancements - which is almost as large as the extra CSA tree of the present invention. On the other hand, the prior art solution allows only the lower degrees of SAD result to be represented by the sum vector alone, i.e.. it involves more common bit degrees in sum and memory number vectors than in the present invention.

It would be possible to present trees that utilize other types of adder than CSA adder, and could be used to reduce the number of operands at an early stage and implement a separate repair tree from which the results are fed to the main compression tree, as in the example described above. However, there are certain advantages associated with the use of CSA adder because they are relatively simple in structure and provide a regular v .: adder allocation and switching arrangement.

It would be possible to implement a premature termination mechanism in a compression tree following the procedure described in prior art US 2003/0043911 A1 • · / "*. The idea is to interrupt the ongoing SAD computation if * · · ♦ · ϊ 25 mapped SAD values exceed a predetermined, fixed threshold value, but omitting 1-3 MSB in this way would, however, allow only very small savings in the main compression structure, whereas a larger number of bits i.:*: omitting would easily cause excessive restrictions on the SADs to be processed.

, · * '*: Reducing the bit width leaves the compression structure height unchanged.

··· 30 A full 16-bit structure implementation is a very workable solution; whatever I want- '·· *! the desired output bit of the accumulated memory number vector may be used as an interrupt that will emit an early termination.

• · ♦ • · «

Figure 11 illustrates, by way of example, a third-order, i. minimum SAD - **** entrepreneur, simple implementation. Note that the proposed implementation does not include the determination of the 35 motion vectors, which are the responsibility of another suitable circuit member. Also, the implementation of Fig. 11 117956 van 11 does not include any premature termination mechanisms, more specifically below.

The compressed current sum and memory number vectors are received through the SAD_S and SAD_C inputs. Comparison with the previously stored minimum SAD value starts with 5 bit inversion of the previously stored minimum SAD inverter 1101. Using a 15-bit CSA, the 1102 bit inverted minimum SAD value is accumulated in the SAD S and SAD C vectors. The continuous one-bit insertion required in the two complement representations is handled by OR port 1103, which is coupled to receive the least significant 10 bits of the bit-inverted minimum SAD and the current SAD_S and send the result as an additional LSB to increase the CSA: n 1102 left (memo number) outputs. CSA compression produces two difference vectors dif_Sis..i and dif_ci6..i which are summed in a 16-bit adder 1104. The adder may be somewhat reduced because only the most significant sum bit (s16) is needed at its output. This bit indicates the sign of the subtraction.

15 Since the calculation of one SAD value extends over several cycles, the control input CMPR is needed to indicate the correct time for the SAD value comparison. A gate structure having a NAND port 1105 and an AND port 1106 takes into account both the CMPR signal and the ZERO_SAD input signal, which indicates whether this is the first SAD value calculation, so that there is no previously stored minimum SAD-20 value. If the most significant sum bit s16 is '0' or if the ZERO_SAD bit is '1' • »\ v during comparison, then the 13 most significant bits of the current SAD value, calculated in parallel in the 13-bit adder 1107, and the 3 least significant bits , taken directly from SAD_S (because the corresponding bit stages were missing · ***; SAD_C), are stored in register 1108 as a ready new minimum SAD value.

M ·:, ·. 25 The multiplexer 1109 recycles the old minimum SAD or stores a new one, depending on the .1 · 1 ·. 'Signal NEW MIN. Inverter 1110 inverts the incoming ZERO_SAD control bit to ensure correct operation.

Μ, ϊ The new minimum SAD value activates both two output signals SAD_RDY and MIN_RDY, which are stored in output registers 1111 and 1112. If the new value was not the first of y .. '30, and not lower than the previous minimum value, only SAD_RDY is activated.

The interdependencies between the CMPR, ZERO_SAD, Si6, SAD_RDY, and MIN_RDY bits are shown in the following table.

«· *» · • · · M · «· · * 1 • · * ·«

Table 10: 17 117956

CMPR ZERO SAD s16__SAD RDY MIN RDY

0__0__0__0__0 0__0__1__0__0 o__i__o__o__o 0 __1__i__g__o 1 __o__g__i__1 1__g__i__i__o 1__i__g__i__1 Γ 1 l 1 I 1 1 1

Figure 12 illustrates a minimum SAD determinant in which a number of early termination mechanisms are implemented. The minimum SAD determination proceeds essentially in the same manner as described above with respect to Figure 11. The first premature termination mechanism is based on the fact that even before the current SAD value is complete (i.e. before the CMPR control signal is activated), if the most significant sum bit s ^ becomes '1', the current cumulative SAD has already exceeded the previously stored minimum -SAD value. Therefore, the most significant sum bit Si6 is provided as 10 additional output signals SAD_EXC via the output register 1201. AND port 1202 performs an AND operation between the Sie bit and the inverted ZERO_SAD control bit, whereby the SAD_EXC output remains in the state '0' when the first SAD value is lowered by * * * s /. ' a. Compared to Figure 11, the mechanism for detecting a minimum-SAD overrun requires only one AND port and one 1-bit register increment.

15, and no further delay. When the SAD_EXC output receives a value of '1', it is intended * ··· * that the control algorithm stops computing the current SAD.

φ ·

»» I

• · · M * ». · **. Comparing the current SAD value with a fixed threshold value makes sense only substantially when calculating the first SAD value, i.e. when the ZERO_SAD control bit is ak-. ·. tive. Therefore, the implementation of Fig. 12 includes a ZERO_SAD control bit controlled by a · · · · · · · · · · · · · · · · · · · · 20 20 20 multiplexer 1203, which selects either an inverted previous minimum SAD value or a · · **: · * TH input and Line. The AND port 1205 and the output register 1206 provide the TH EXC indication in the same *: * · manner as described above for the SAD_EXC output, except that the AND port. The 1205 receives a non-inverting ZERO_SAD bit from one of its inputs, so that the output of 25 TH_EXC outputs is only possible during the first SAD value calculation. An additional area requirement for this mechanism is 16 NOT ports, one 18 117956 16-bit multiplexer, one AND port, and one 1-bit register. The delay increase corresponds to the delay caused by the multiplexer 1203. .

The implementation of the threshold override detection also supports comparison with multiple thresholds. Once the current threshold is exceeded, the next higher threshold can be input via the TH input during the next period. A one-period delay between successive threshold comparisons prevents consideration of the remaining higher thresholds if the current threshold was only exceeded during the last period before the SAD was completed. However, this is not a serious disadvantage since thresholds are usually only used to speed up algorithm performance. Thus, an unmatched higher threshold for an object can, at worst, cause unnecessary computation, but the correct result is still achieved.

It would be possible to perform the detection of a threshold overrun in parallel by duplicating the reference portions of the minimum SAD for each desired threshold level. A parallel threshold indication would reduce the delay by an unnecessary selection multi-15 plexer, and completely eliminate the delay between successive threshold comparisons. However, the resulting increase in circuit area would be relatively large due to duplicate reference logic.

The third premature termination mechanism is based on the deliberate preference for the first, i.e. the SAD-20 value of the stationary candidate macroblock. This will subtract the predetermined parameter input -ZERO BONUS from the SAD value of the zero · · · motion vector. In practice, the -ZERO_BONUS value is set to AND-

• I I

1 through the gateway enable member 1207 to the CSA 1208, which sums it to its current SAD value. The AND ports of the enabling member 1207 receive their second input / ·· * input, the activation input, from the ZERO SAD control input, whereby the -ZEROJ30NUS input min. ...: control bit is active. In known solutions, for example, a suitable zero bonus is one hundred when using the so-called "zero" bonus. diamond search algorithm. -ZEROJ30NUS value: f: may be a fixed constant at design stage, or may be a runtime parameter: * '* · controlled by a digital video encoding control algorithm. The * · «30 null bonus mechanism of Fig. 12 represents an increase in area required by the 16 AND gates and one 16-bit CSA, and no delay increase at all.

The interdependencies between the bits CMPR, ZERO_SAD, s16, SAD_RDY, MIN RDY, * * of the implementation of Fig. 12 are shown in the following table.

Table 11: 19 117956

CMPR ZERO SAP s16 SAD RDY MIN RDY SAD EXC TH_EXC

0__0__0__0__0__0__0 0__0__1__0__0__1__0 0__1__0__0__0__0__0 0 __i__i__o__o__g__1 1 __g__g__i__i__g__o 1__g__i__i__g__i__o 1__i__g__i__i__g__o 1 1 1 l 1 l 1

Compared to the known Chen minlmi SAD determiner (see US 5,838,392), the arrangements of Figures 11 and 12 can be said to have the drawback that they require 5 one additional 15-bit adder (or 13-bit adder in Fig. 11), which is However, the advantage of the arrangements shown in Figures 11 and 12 is that they require only about half of the registers and selection logic used to store the minimum SAD value, and only about half of the inversion of the minimum SAD value. 10 inverting logic. Minimum SAD comparison is also faster because the CSA + OR combination is faster than the 4: 2 compressor. A narrower adder is sufficient for the sum of the difference vectors, and the actual SAD value is immediately used. v. here, which is an advantage because it is needed, for example, to select between INTRA and • 11 'INTER coding modes.

Fig. 13 shows the difference value units of Fig. 7, the ij 'compression structure of Figs. 8 and 9, and the minimum SAD determinant of Fig. 12, inserted in the overall structure shown in Fig. 6. Differential value units 602 occur in pairs, and each pair has a half - adder 721 two - bit,. ten correction bit vectors. First degree 601 and second degree, ·· *. The registers 1301 between the 20 paths 611 take care of transmitting the uncorrected difference values and the correction bit vectors. Similarly, second order 611 and third order 621 have registers 1302 for transmitting the compressed SAD_S and SAD_C values. The output registers are shown in Figures 11 and 12 as parts of the minimum SAD- •) · descriptor, so they are not shown separately in Figure 13. The first step 601 • · · 25 receives 32 operands, which are 16 pixel values from each current and condition - *** ' macroblocks. The second step 611 receives 26 operands which are 16 differential values, 8 correction bit vectors, and two feedback values from the outputs of the second step 611 20 117956. Further, the second step 611 receives the control input INIT. The third step 621 receives the compressed SAD_S and SAD_C values, a feed back value MIN_SAD from its source, a threshold TH, a zero bonus value -ZERO_BONUS, and control signals CMPR and ZERO_SAD. The outputs of the third step 621 5 are the MIN_SAD value and the indicator outputs SAD_RDY, MIN_RDY, SAD_EXC and TH_EXC.

Parts of the overall structure shown in Figure 13 could be replaced by alternatively chosen solutions. For example, if for some reason it were desired to explicitly use Chen's difference value units (see Figure 2) instead of the first order 601 of the embodiment of the present invention, they could be used provided that Chen's correction bits were converted to correction bit vectors in the auxiliary medium before 611. Chen's compression structure instead of the second order 611 according to the embodiment of the present invention would also be possible using the intermediate, which this time should intercept the correction bits from the first order before combining them into the correction bit vectors. Also, the prior art minimum SAD detector could be used in place of the third order 621 of the embodiment of the present invention by making small changes that would be readily accomplished by one skilled in the art. However, replacing parts of the new and inventive solution described above would inevitably lead to lower performance and less favorable performance. . solution.

• · ·.

• * · • ·

Methods for deriving theoretical delay and area estimates · * · 'are known. to the invented motion estimator. Area cost for basic ports with n inputs, • ·. ···. is n cost units (CUs) except for XOR and XNOR ports for which it is 2n CUs.

In turn, the delay cost for all gates used is 1 τ. Usually * · · registers, connections, and fan-out / fan-in factors are not included in the calculations. Due to these assumptions, the results obtained ***** are better for comparison purposes than for use as independent absolute measurements.

• · · • · «

Adapters typically represent a large portion of the delay and area costs.

* · * 30 Therefore, there are three types of adder with different properties: * * ** ·· [RCA or ripple carry adder, CLA (carry look-ahead adder) and CSA \ * (carry save) adder. In addition, in addition to the n-input port versions (CLA (n)), the 2-input port versions (CLA (2)) of the CLA admixtures are separately analyzed because *** is used. the effect of the gate width at the center is essential to the CLA. The difference with CLA versions is that the n-input ports used in CLA (n) are replaced by 2-input port trees in CLA (2). It is noteworthy that the direct replacement of n-input ports with 2-input port trees leaves 21 117956 spaces for CLA (2) area optimization. However, such optimization is not taken into account in these calculations.

The assumption is based on the assumption that the delay and surface costs for one half adder are 1 τ and 6 CU, whereas the corresponding figures for the full adder are 3 τ 5 and 14 CU. In the analysis, it is assumed that all the adders contain only the logic needed to produce the requested result. In other words, the logic associated with unused input and output ports has been removed.

The upper and lower diagrams in Figure 14 show theoretical delay and area estimates for different estimation units. Column 10 with a single slash represents a RCA / CSA implementation, a white column represents a CLA (2) / CSA implementation, a cross-hatched column represents a CLA (n) / CSA implementation, and a column with a double slash represents a CSA implementation. In each unit, the sum repute type changes only between RCA and CLA. These adders are the adder units 701 and 711 in the difference value unit of Figure 7 and the adder units 1104 and 1107 in the minimum SAD-15 determination unit of Figure 11.

Let us first consider the analyzed implementations of the difference value unit. In all cases, the area cost is calculated for 16 units. The invented CLA-based unit is the preferred solution for high-performance applications, while: V: 20 the invented RCA-based unit offers the most surface-efficient implementation. The pre-*; y: compression building unit containing only the CSA adder is a very efficient solution in terms of execution speed and area efficiency. Finally, a comparison between RCA and CLA-based minimum SAD determinants reveals, '* 1 that the delay increase in RCA-based implementations is much more significant than the surface / 25 down savings. Therefore, a CLA-based minimum SAD descriptor is the recommended implementation.

• · • · · * ·

Based on the results of the analysis, two effective pipeline arrangements are suggested; for the larger units. The first one follows the system shown in Figure 13 • · ·. ···. processing. In this three-stage arrangement, the RCA-based difference units are fast enough for the first degree. The pipeline degrees are theoretically well balanced, since the combination delay of each of the units in question is close to 19 τ. For CLA-based configurations, the mean CLA (2) and CLA (n) theoretical delay estimates are used. The latency of the structure is three clock cycles. Another proposed pipeline arrangement contains only two pipeline degrees. The execution rate of this second arrangement is increased by using CLA-based difference values. 35 According to theoretical delay values, the optimum position of the available pipeline intermediate is 22 117956 before the final CSA of the compression structure. Thus, the theoretical combination delay of both pipeline stages is about 23 τ.

For the proposed 3-step and 2-aster structures, surface and timing results based on logic synthesis are presented. Synopsys Design Compiler is a known tool used in the synthesis of ASIC-5, and the technology used can be assumed to be a 0.18 micron CMOS process. The adders included in the proposed architectures are implemented with special Synopsys DesignWare components. Strictly speaking, RCAs and CLAs have been implemented with known DW01 j-p1 and DW01_cla components. The CSAs, in turn, consist of 1-bit DW01_rpl summers. The area metrics (ie-10 number of volumes) are based on equivalent 2-input NAND ports, while the delay values correspond to the critical path of the pipeline architectures. The registers are also included in the delay and area metrics.

Using the selected technology, the proposed 3-step SAD architecture is capable of operating at 780 MHz. Implementing this maximum frequency architecture, the mak-15 receives less than 5600 NAND ports. It is clear that compromising the operating frequency requirements will increase the surface area efficiency of the architecture. The same architecture at 580MHz costs 4200 NAND ports. Further, the 380 MHz operating frequency is achieved by an architecture having a minimum surface area of about 4000 NAND ports.

On the other hand, the proposed 2-tier architecture can be clocked up to 700 MHZ on a 7400 NAND-20 port. The 520 MHz and 360 MHz operating frequencies, in turn, are achieved at 4900 • · v .; and 3900 on the NAND port. The conclusion of the study is that the proposed 3-step architecture is a recommended implementation for high performance and area efficient systems with acceptable three cycle latency. The proposed 2-step sheet operation, on the other hand, is more suitable for low latency high-end systems.

• * • · *: · :; Figure 15 shows a video encoder according to an embodiment of the invention. Incoming • · · * ··: video signal 1501 is applied to motion estimator 1502 which performs macroblock comparisons to determine motion vectors. The latter are exported to motion compensator 1503, which essentially outputs the macroblocks from the previous frame, i * ": as indicated by the motion vector. The difference between the original frame and the frame indicated by the motion vectors is calculated in adder 1504, whose output thus forms a prediction. The prediction error is computed with DCT (Discrete Cosine Conversion) coefficients in the 'DCT encoder block 1505, and the calculated coefficients are quantized in the quantizer j #: *: 1506. From there, the quantized DCT coefficients are exported to a Huffman / Run-Length encoder 1507 whose output is encoded by videoign.

* * ♦ 23 117956

For motion compensation, inverse quantization and DCT decoding are performed in the respective blocks 1509 and 1510. Adder 1511 and temporary frame memory 1512 are required to properly input feedback information to motion compensator 1503. Output of motion compensator 1503 is coupled to adder 1511 and space 5 the latter provides information on the content of the reference frame.

The control unit 1513 controls the operation of the video encoder. One of the main functions of the control unit 1513 is to make decisions on the coding mode to be selected for each frame: intra-coding (i.e., 'independent' or 'self-linked' coding) for frames that would be difficult to code by predicting other frames and various forms of inter-coding for predictable frames. The control unit 1513 also performs any software or firmware based control routines affecting the encoding process. The functions of the control unit 1513 may not be implemented in one centralized circuit element, but may be distributed in two or more distributed control sub-units 15.

1 '

The present invention mainly affects the motion estimator 1502, which in the video encoder according to an embodiment of the invention comprises the above described difference units, a compression structure and a minimum SAD determiner. However, the invention also has an effect on the control unit 1513, particularly if the early termination criteria described above with reference to Figures 12 and 13 are used. Un-v \: simple time-based control signals, such as CMPR, INIT, and ZERO_SAD, may come from the timer unit included in the motion estimator 1502, or may be outputs to the motion estimator 1502 of the ohm unit 1513. Parameter values such as • ·. · **. These can also be programmable, such as TH and -ZERO_BONUS, typically coming from: 25 control units 1513 or registers controlled by control unit 1513. '• · · * • ♦ · · • · ·

The outputs SAD_RDY, MIN_RDY, SAD_EXC, TH_EXC and MIN_SAD are preferably controlled from the motion estimator 1502 to the control unit 1513, which makes control decisions based on the values of said outputs. For example, activated SAD_EXC

The output bit indicates to the control unit 1513 that the current computed SAD has already exceeded 30 previously calculated minimum SADs, so that the control unit 1513 can command the movement es - ** '. simulator 1502 to stop computing prematurely and proceed to calculate the next SAD. The control unit 1513 may also be programmed to monitor the MIN SAD values it has received from the motion estimator 1502, for example! inter / intra coding decisions are based on whether or not the minimum SAD values are within certain limits. The structure and operation of the control unit 1513 will be apparent to one skilled in the art on the basis of the foregoing explanations.

24 117956

It should be noted that the foregoing description contains illustrative examples, which do not limit the applicability of the invention. For example, the invention is by no means limited to comparing 16 pixels of two macroblocks of consecutive picture frames. Simultaneously, the number of pixels to be compared may be any other, the frames to be compared may have a relationship other than succession, and "pixels" may be anything other than the elements of a two-dimensional graphic representation. As a simple generalization, the term "macroblock" can be replaced by the term "regular set of multi-bit values", whereby the invention is applicable to all kinds of cases intended to determine the extent to which a similar set of jo-10 is written with another. The term "pixel" may be understood to describe a dimensionless entity such as a sample of a digital audio signal compared to another digital audio signal, or a three or more dimensional entity such as a "voxel" or "volume pixel" which is an atomic component of three-dimensional digital images. The pixel values in the photo frames are always 15 positive, which can be considered as a postulate in an image editing application; if the proposed solution were to be applied for another purpose where the sign of the values being compared could vary, some preprocessing would be needed to ensure correct operation.

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Claims (19)

1. A circuit for calculating the sum, hereinafter referred to as the SAD value, of absolute difference values between two regular quantities of multibit values, the circuit comprising: - a plurality of units of absolute difference values (602), each of which is. V. coupled to receive a multibit value from each of two quantities of regular *, ·, multibit values, and arranged to generate as an output an uncorrected abso- lution difference of two multibit values and a correction bit value, such as indicates the correction of the uncorrected absolute difference value, - a compression structure (611), coupled to receive uncorrected absolute difference values and indications of the correction bit values from the units of absolute ··· difference values (602) and arranged to form a sum vector and a transfer digit vector, which together represent the sum of the outputs of units:> t (s) of absolute difference values (611); *** characterized by the compression structure (611) comprising: * ·· y. 30 - a main compression tree (612) coupled to receive uncorrected absolute *** \ difference values from the units of absolute difference values (602), and wherein the main compression tree (612) comprises a plurality of interconnected adder and is arranged to compress a first set of input values to a second set. ***; output values, and ··· '35. a correction tree (613) coupled to receive indications of the correction bit values from the units of absolute difference values (602), and which correction tree (613) comprises a plurality of interconnected adder and is arranged to compress a third set of input values to a fourth set of output values, and which correction tree (613) is coupled to provide its output value to the adder of said main compression tree (612). 5 2. A circuit according to claim 1, characterized in that the couplings between said adder of said main compression tree (612) form a composition consisting of the piano such that the adder of the first plane is coupled to receive the eating utensils part of said main compression tree (612). the adder of the last plane is coupled to receive at least part of the output values of said main compression tree, and the adder of the second and subsequent planes has inputs connected to the outputs of the adjoining plane's adder. Circuit according to claim 2, characterized in that said first branch of said main compression tree (612) comprises six adder, said second pad comprises four adder, the third plane comprises three adder, the fourth plane comprises two adder, the fifth plane comprises an adder and the sixth plane, which is said last pane, comprises two adder, - each said adder of the main compression tree (612) comprises three inputs, a transfer digit output and a sum output, - said adder of said correction tree (613) a composition consisting of the piano such that the adder of the first plane is coupled to receive the input memory of a part of said input values of said correction tree (612) and that: the adder of the second plane has the inputs connected to the outputs of the preceding planes adder, ** ··: - said correction tree (613) said first piano comprises television an adder, of: each having three inputs, a transfer digit output and a sum output, * ··: ... - the second tab of said correction tree (613) comprises two adder, one of which has two inputs, a transfer digit output and a sum output , and the: 30 others have three inputs, a transfer digit output and a sum output · ** '; - the third pane of said correction tree (613) comprises an adder, which comprises three inputs, a transfer digit output and a sum output, and the adder of the main compression tree and the correction tree are connected in a manner which shown in Figures 8 and 9.: *. 35 • * *, * ···. 4. A circuit according to claim 3, characterized in that said adder of said main compression tree and said correction tree is a carry save type adder. 32 117956 5. A circuit according to claim 1, characterized in that the correction bit values of a pair formed by two adjacent units of absolute difference values (602) are cumulated into the correction bit vector before entering the compression structure (611), the indications of the correction bit values being coupled from the units. of absolute difference values (602) to the compression structure (611) are said correction bit vectors. 6. A circuit according to claim 5, characterized in that it comprises a half-adder (721) for each pair formed by the adjacent units of absolute difference values, said half-adder (721) being coupled to receive said correction bit values and arranged to change said correction bit values to said correction bit vectors. The circuit according to claim 1, characterized in that each unit of absolute difference values comprises: - an adder (701, 711), with a direct input to a multi-bit operand and an inverting input to a second multi-bit operand and a sum output with as many bits as there are bits in said multi-bit operand, 20. a transition digit output, arranged to form a bit value "1", if the operand supplied to said direct input is greater than the operand passed to said inverting input, and the bit value " 0 "in other cases, and · · II '- as many XOR ports (702, 712) as there are bits in said adder output, each XOR port (702, 712) having an input coupled to receive a bit of said sum output, and a second input coupled to receive an inverted value of said transfer digit output. • · * · • «· ··» · • · ·: ... i 8. A circuit according to claim 1, characterized in that it comprises a minimum SAD definer (621) coupled to receive SAD values formed in said compression structure (611) and arranged to compare a quantity successively. ** ·. calculated the SAD values to find the lowest of them. The circuit according to claim 8, characterized in that said minimum SAD definers (621) comprise::: * · 35 - a register (1108) arranged to store the previously found minimum SAD value, «·« ·. ** ·. a sum vector input and a transfer digit vector input coupled to receive a first output value and a second output value from said main compression tree (612), - a three-input carry save adder (1102), the first of which is coupled to receive a sum vector via said sum vector input, one is coupled to receive a transfer digit vector via said transfer digit vector input and one is coupled to receive said previously found inverted value for minimum SAD, and which carry save adder (1102) is a sum output and a transfer digit. output, - a first adder (1104) coupled to receive operands from said sum and transfer digit output of said carry save adder (1102) and having a single byte thread arranged to indicate, by the addition of said operands, whether the value represented by said first and second output values from the main compression tree (612) is smaller than the previously found minimum SAD value, - arrangement (1105, 1106) of logic gates arranged to generate an indication where said single bit adder (1104) indicates the SAD value represented by said first and other output values obtained from the main compression tree (612) are lower than the previously found minimum SAD value at a specified suitable comparison time, - a second adder (1107) arranged to calculate the SAD value of said sum and transfer digit vectors, 20. a multiplexer (1109) coupled to receive said indication from the arrangement of said logic port (1105, 1106) and to respond to an active indication by storing the SAD value calculated with said second adder (1107) in said register (1108) and missing of an active indication by storing said time, the minimum SAD value found used in said register (1108). 25 A circuit according to claim 9, characterized in that said minimum SAD * · »· * definition (621) comprises: • · · - a ZERO_SAD input, arranged to convey an indication of whether sum - and the transfer digit vectors are connected in said sum and transfer digit * / 30 vector inputs to the SAD value which connects to two regular quantities: ***: multi-bit values, which are not associated with relative motion in the frame, and y .. ' - a bonus input and an activation arrangement (1207) formed by the logical *** ports, which respond to the indication in said ZERO SAD output by activating the inclusion of the bonus value via said bonus input in the calculation of: 35 SAD value, which SAD value is connected to two regular quantities of multi-bit values, which are not associated with relative motion in the frame. A circuit according to claim 9, characterized in that said minimum SAD definers (621) comprise: - a threshold value input coupled to receive a threshold value, - a selection multiplexer (1203) arranged to controllably replace the coupling of the previously found mini SAD. - the threshold value coupling via said threshold value input to the input of said carry save adder (1102), and - an output register (1206) connected to the threshold coupled to receive and transmit an indication when said first adder (1104) said single bit input the value represented by said first and second output values 10 from said main compression tree (612) is higher than said threshold value. The circuit according to claim 11, characterized in that - said minimum SAD definition (621) comprises a ZERO__SAD input arranged to convey an indication of whether the sum and transfer digit vectors in said sum and transfer digit output represent an SAD -value connected to two regular quantities of multi-bit values not associated with relative motion in the frame, and - said selection multiplexer (1203) responds to the indication in said ZERO_SAD input. 20 A circuit according to claim 9, characterized in that said minimum SAD definers (621) comprise: • · · - a ZERO_SAD input arranged to convey an indication of whether the sum and transfer digit vectors of said sum and transmission digit vector inputs represent an SAD value that connects to two regular * *! * ·· * amounts of multibit values not associated with relative motion in the frame, and: - an output register (1201) connected to the minimum SAD value and linked receiving and transmitting an indication, wherein said single bit adder (1104) said bit bit thread indicates that the SAD value represented by said first and second output values received from the main compressor tree (612) is higher than said timestamp: ***: donors found the minimum SAD value at a time when the sum and transfer digit φ · · vectors in said sum and transfer digit entries do not represent *** \ SAD value connected to two regular quantities of multi-bit values that are not * · * ··> associated with relative motion in the frame, which is different from the specified comparison time *. • · · * Digital video codecs for encoding a digital video signal, characterized in that it comprises a circuit according to claim 1. 117956 A method for calculating the sum, hereinafter referred to as the SAD value, of the absolute difference values between two regular amounts of multibit values, wherein in the process: 5. (602) differences between multibit values taken in pairs from the corresponding locations of said two regular quantities are calculated; thus, uncorrected absolute difference values and correction bits are formed, and - the calculated uncorrected absolute difference values and correction bits are compressed (611) into SAD values; Characterized in that - as part of said compression (611), the correction bits are initially compressed separately from the compression of the uncorrected absolute difference values (612) and the compressed correction bits are measured at given locations in the main process comprising compression (612) of the absolute difference values. 15 Method according to claim 15, characterized in that the correction bits are taken from the calculation (602) of two adjacent absolute difference values and said correction bits are cumulated (721) in the correction bit vector before they are brought to the compression of the correction bits (613). 20 The method according to claim 15, characterized by comparing a quantity of: 1: 1 · successively calculated SAD values to find the lowest of them. • · · • · · 1 18. A method according to claim 17, characterized by prioritizing a SAD value which is connected to two regular quantities of multi-bit values, which are not • 1. "In the context of relative movement in the frame. • · 1 • · · • · · · • 1 · • · * ·· 2 3 19. A method according to claim 17, characterized by comparing the SAD value connected to two regular quantities of multi-bit values, which are not associated with relative movement in the frame, with a threshold value, and deciding on further measures depending on if the SAD value is lower or higher than. ···. said threshold value. • · t · «* ·· 2 · '* 1. 1 • · * · · • · · • · 1 · · 2 * · 3