FI20040624A - Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten - Google Patents

Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten Download PDF

Info

Publication number
FI20040624A
FI20040624A FI20040624A FI20040624A FI20040624A FI 20040624 A FI20040624 A FI 20040624A FI 20040624 A FI20040624 A FI 20040624A FI 20040624 A FI20040624 A FI 20040624A FI 20040624 A FI20040624 A FI 20040624A
Authority
FI
Finland
Prior art keywords
fault diagnosis
logic programs
editing logic
editing
programs
Prior art date
Application number
FI20040624A
Other languages
English (en)
Swedish (sv)
Other versions
FI20040624A0 (fi
Inventor
Jari Paanasalo
Timo Virtanen
Original Assignee
Metso Paper Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Metso Paper Inc filed Critical Metso Paper Inc
Priority to FI20040624A priority Critical patent/FI20040624A/fi
Publication of FI20040624A0 publication Critical patent/FI20040624A0/fi
Priority to DE102005018725A priority patent/DE102005018725A1/de
Priority to US11/119,477 priority patent/US20050268169A1/en
Publication of FI20040624A publication Critical patent/FI20040624A/fi

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3323Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
FI20040624A 2004-04-30 2004-04-30 Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten FI20040624A (fi)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FI20040624A FI20040624A (fi) 2004-04-30 2004-04-30 Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten
DE102005018725A DE102005018725A1 (de) 2004-04-30 2005-04-22 Verfahren und System zum Aufbereiten von Logikprogrammen für Fehlerdiagnostik
US11/119,477 US20050268169A1 (en) 2004-04-30 2005-04-29 Method and system for editing logical programmes for trouble diagnostics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20040624A FI20040624A (fi) 2004-04-30 2004-04-30 Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten

Publications (2)

Publication Number Publication Date
FI20040624A0 FI20040624A0 (fi) 2004-04-30
FI20040624A true FI20040624A (fi) 2005-10-31

Family

ID=32104243

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20040624A FI20040624A (fi) 2004-04-30 2004-04-30 Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten

Country Status (3)

Country Link
US (1) US20050268169A1 (fi)
DE (1) DE102005018725A1 (fi)
FI (1) FI20040624A (fi)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL244565A (fi) * 1959-08-19
US5258919A (en) * 1990-06-28 1993-11-02 National Semiconductor Corporation Structured logic design method using figures of merit and a flowchart methodology
WO1995027236A1 (de) * 1994-03-31 1995-10-12 Siemens Aktiengesellschaft Verfahren zur automatischen diagnose von störungsfällen
JP2776262B2 (ja) * 1994-08-18 1998-07-16 日本電気株式会社 論理回路合成方法及び装置
US5848137A (en) * 1997-05-22 1998-12-08 Hsiao; Ray-Ling Device and method for processing multimedia message

Also Published As

Publication number Publication date
US20050268169A1 (en) 2005-12-01
FI20040624A0 (fi) 2004-04-30
DE102005018725A1 (de) 2005-12-01

Similar Documents

Publication Publication Date Title
GB2453450B (en) System and method for monitoring a well
NO20054549D0 (no) A method and a system for secure transactions
GB2442425B (en) Non destructive inspection system and associated method for structural health monitoring
ZA200708324B (en) A system and method for railyard planning
GB2431262B (en) System and method for logging recoverable errors
EP1941389A4 (en) SYSTEM AND METHOD FOR CREATING A DISPLAY LIST
EP1999662A4 (en) SYSTEM AND METHOD FOR CREATING DESIGNS
ATE518584T1 (de) Tönungsmaschinensystem und verfahren
EP1933957A4 (en) SYSTEM AND METHOD FOR GAMING CONTENT MANAGEMENT AND CONFIGURATION SYSTEM
ZA200708898B (en) A method and arrangement for providing context information
GB2444222B (en) Inspection system for inspecting a structure and associated method
EP1951470A4 (en) SYSTEM AND METHOD FOR PROVIDING POWER SIGNALS AND CONTROL THROUGH A ROTATING INTERFACE
DE602006009212D1 (de) Gerät, System und Verfahren für einen Grafikspeicher-Hub
HK1134368A1 (en) System and method for providing redundancy management
FI20040110A0 (fi) Menetelmä ja järjestely verkkovaihtosuuntaajan yhteydessä
GB0811010D0 (en) A method, system and software for talent management
EP1901168A4 (en) SYSTEM AND METHOD FOR DEBUGGING AND RELATED PROGRAM
DE602006018415D1 (de) System und Verfahren zum Ummanteln von Fäden
EP2007153A4 (en) METHOD AND APPLICATION FOR MONITORING SYSTEM COMPOUNDS
EE200500038A (et) Süsteem ja meetod ressursside haldamiseks ja juhtimiseks
FI20041563A0 (fi) Menetelmä, järjestelmä ja tietokoneohjelma viihteellisten sovellusohjelmien tuottamiseksi, tarjoamiseksi ja ajamiseksi
FI20021112A (fi) Menetelmä ja järjestely paikannuksen suorittamiseksi
FI20040624A (fi) Menetelmä ja järjestelmä logiikkaohjelmien muokkaamiseksi vikadiagnostiikkaa varten
FI20045238A (fi) Menetelmä ja järjestelmä viallisen vaiheen tunnistamiseksi
DE502004009277D1 (de) Fugendichtung und Verfahren zu ihrer Herstellung

Legal Events

Date Code Title Description
FD Application lapsed