FI114588B - power controller - Google Patents

Description

114588

power controller

The invention relates to a method according to the preamble of claim 1 for controlling the AC power supplied to the load by adjusting the phase angle 5 of the AC voltage.

The invention also relates to a power regulator according to the preamble of claim 3 for adjusting the AC power supplied to the load by adjusting the phase angle of the AC voltage.

The AC power applied to the load is generally controlled by interrupting the electrical current flowing through the load 10, whereby the electrical power to be applied to the load is determined by the ratio of the on and off time of the load current and the amplitude of the AC voltage. In most AC applications, the load current switching cycle occurs once per AC half-cycle. Such a device is often referred to as a phase angle controller. The phase angle regulator can be used to control, for example, lamps, motors and heating elements.

All real loads are reactive - they have a resistive, capacitive and inductive component. If the capacitive and inductive parts are very small compared to the resistive one, the load is called resistive in nature, for example a light bulb. Capacitive in nature is defined as a load which, in addition to the 20 resistive parts, has substantially capacitance (e.g., an electronic transformer for low voltage halogen gene bulbs) and substantially inductor, respectively. · Loads containing dance are referred to as inductive in nature (for example, a motor, · · engine or transformer).

t • 1 *, 'The current i passing through capacitance C is generally expressed by the equation: 25 i (t) = C du / dt, where (1)' u is the voltage across capacitance C and t is time. Considering equation 1, it is found that it is advantageous to adjust the capacitive load by means of a phase angle regulator: which switches the load current on the mains voltage at zero. In this case, the charge current i of capacitance C, which depends on the change rate of the voltage »_ ': du / dt, remains small. Such an adjustment method is hereinafter referred to as trailing edge adjustment. One device using trailing edge adjustment with a switch component as a FET or channel transistor is disclosed in International Patent Application Publication No. WO 9322826.

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The voltage u over inductance L is generally expressed by the equation: u (t) = - L di / dt, where (2) i is the current through inductance L and t is time. Considering equation 2, it can be seen that the high change rate current changes di / dt cause induct-5 dance L over high voltage u. In order to avoid this voltage peak, it is advantageous to adjust the inductive load by cutting off the load current at the zero point of the current flowing through the load. Such an adjustment method is hereinafter referred to as a front-edge adjustment, and a well-known bidirectional thyristor, or triac control, utilizing it is described, e.g. in United States Patent 10 US 6175195.

The prior art techniques described above have their drawbacks and problems: - Conductive Triac cannot be brought to a non-conductive state until the current through the triac has dropped to zero. The triac controller therefore requires a fuse for short-circuit and overcurrent protection. In practical electrical installations, it has been found that changing the internal fuse of the device 15 is a common reason for starting an electrician's installation. As a result, a fuse in a short circuit causes additional costs to the end user of the device, which are often higher than the purchase price of the device.

,. - Triak's switching speed is relatively high and cannot be actively adjusted. Electrical; ; Due to the requirements of Magnetic Compatibility (EMC) 20, the known triac regulator includes a choke which limits the current rise rate to the allowable level. The said choke causes power losses in the power circuit which increase the temperature of the device.

* · :: In addition, the throttle is costly, large in size, demanding space for the stylish device, and has been found to distract the end user due to its' 25 female hum.

. The FET semiconductor controller mentioned in WO 9322826 does not necessarily include a fuse or a choke, but it is a rear edge controller. Therefore, by virtue of Equation 2, it is not suitable as a power regulator for an inductive I load of an inductive nature. The illustrated controller can be converted to use the leading edge • adjustment mode, but requires accurate measurement of the current flowing through the controller, resulting in more complex circuit design and thus increased device production costs.

3, 114588

It is an object of the invention to provide a method and apparatus for adjusting the AC power supplied to a load which solves the above problems and which allows adjusting the AC power of a resistive and inductive load by means of two power transistor switches, in particular MOSFETs.

The method of the invention for adjusting the AC power supplied to the load by adjusting the phase angle of the alternating voltage is characterized in what is set forth in claim 1. The power regulator according to the invention is in turn characterized by what is set forth in claim 3. Preferred claims

The invention provides several advantages: - It is possible to provide short-circuit protection without a fuse in the device according to the invention. This simplifies the mechanical structure of the device and lowers the operating cost for the 15 end users of the device.

The device according to the invention does not necessarily include a choke. Thus, it is possible to reduce the physical size of the device or, correspondingly, implement a device with a higher power handling capability in the same size range.

·. - Compared to a power control based on a triac switch, especially a dimmer. The device of the invention does not emit audible noise in the human ear in its environment.

* · • \ · - Thanks to auto-commutation, the invention enables the use of a transistor switch: in its front-edge power control, with precise load cut-off:; when the current reaches zero, without the need to accurately measure the load current.

In the following, the invention will be described in detail with reference to the accompanying drawings, in which Figure 1 shows a schematic diagram of a power regulator connected in series with a load and controlled according to the method of the invention; Fig. 2 is a block diagram of a power controller according to the invention; Fig. 3 shows a preferred embodiment of a power controller according to the invention, in particular its control unit; Fig. 4 114588 Fig. 4 shows the curves of voltage and current as a function of time at various positions of the power regulators of Fig. 1 when the load is resistive in nature; and Fig. 5 shows the curves of voltage and current as a function of time at various points in the power regulator of Fig. 1 when the load is inductive in nature.

Fig. 1 schematically illustrates a power regulator 1 by means of which the method of controlling the AC power supplied to the load according to the invention can be implemented. The power regulator 1 comprises a switching unit 2 and a control unit 3 thereof. The power regulator 1 is connected in series with the load L. An alternating current source AC, such as an AC mains, is connected across a series connected power regulator 1 and a load L 10.

The switching unit 2 consists of two switching elements connected to each other and simultaneously to the load L, i.e. the first and second switching elements k1, k2, and the opposite diodes arranged next to them, i.e. the first and second diodes d1, d2. By means of the control unit 3, the switching elements k1, k2 of the switching unit 2 are alternately driven to an electrically conductive state, i.e., a closed state, and a non-conductive state, i.e., an open state, respectively during a half cycle of the supply voltage.

Figures 4 illustrate voltage and current waveforms in conjunction with the power regulator 1 of Figure 1 when the load L is of a resistive nature. The load L '': 20 is then, for example, a light bulb whose luminous efficacy is controlled by adjusting the ac power supplied to it. Fig. 4a shows a graph of the alternating voltage VAC from the AC source AC over several consecutive semiconductors PA, PB, PA, ..., as a function of time t. Figures 4b and 4c show the states of the switching elements k1 and k2 ·. ', Respectively, such that 0 represents the open state of the switch and 1 represents the closed state of the switch. load

! ,, 'The curve shape of the voltage VL over 25 L is shown in Fig. 4d and the load current IL

4e.

; In the method according to the invention, after the time delay ta defined by the first semiconductor AC of the alternating voltage VAC at the first load current zero N1 (time A, Fig. 4a), the first switching element k1 is controlled; 30 while the second switching element k2 is driven to the open state (time B,> I> t »in Figure 4b and 4c). In this case, the load current IL is arranged to pass the first switch; *; through the element element k1 and the forward second diode d2 until the load; the direction of the current current IL changes at the second zero point of the current N2 (time C, Fig. 4a), whereby the direction of the load current IL is reversed with respect to the second diode d2 5 114588, thereby preventing current flow to load L (time C, Fig. 4e). After the time delay ta from the second load current zero point N2 in the second half-cycle PB of the alternating voltage VAC, the second switching element k2 is actuated to the closed state while the first switching element kl is actuated to the open state (time D, Figures 4b 5c). Herein, the load current IL is arranged to pass through the second switching element k2 and the forward first diode d1 until the direction of the load current again changes at the next zero of the current (time E, Fig. 4a). This zero point N3 corresponds to the first zero point N1 with respect to the change in load current IL, where the direction of the load current IL is reversed with respect to the first 10 diodes d1. The first diode d1 thus prevents the current from passing through the load until the above steps of operation are repeated in the third semiconductor corresponding to the first semiconductor PA. After a time delay ta determined from the current zero point N1, N2 over the load L, the load voltage VL according to Fig. 4d is applied up to the next current zero point N2, N3. With a resistive load L, the load current 15 IL follows in parallel the load voltage VL as shown in Figures 4d and 4e. The load voltage VL follows the alternating voltage VAC of the alternating current source AC at time intervals B-C and D-E.

From the alternating voltage VAC of the AC source AC, the following positive PA and negative PB semiconductors are determined, based on which the control of the switching elements k1, 20 k2 is implemented by the control unit 3. The forward directions of the diodes d1, d2 in the switching unit 2 are taken into account. coupled to one of the anodes and between the coupling elements k1, k2. They are in the forward direction away from the common coupling point. This switching point is also used; , the virtual unit VM of the control unit 3. In this case, coupling elements k1, k2 '; 25 is alternately controlled such that the first coupling element kl leads to an alternating current! ! VAC in the positive semiconductor PA after the time delay ta and, respectively, the second switching element k2 in the negative semiconductor PB after the time delay ta.

Alternatively, the coupling element 2 of the switching unit 2 of the embodiment of Fig. 1: the diode pairs k1, d1 and k2, d2, respectively, can be arranged to be interchanged, whereby the second switching element k2 and the other diode d2 are alternating current; on the AC side and the first switching element kl and the first diode dl

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are on the load side L. In this case, the diodes d1, d2 are connected with respect to each other such that their cathodes are connected to each other and further between the switching elements k1, k2 in a virtual earth VM. They are downstream to a common switching point, i.e., virtual-slime VM. In this case, when viewed from the AC source AC, the switching elements 11 k88, k1 are controlled such that the first switching element k2 drives the alternating voltage VAc with a negative semiconductor PB after a time delay ta and a second switching element k1 with a positive semiconductor PA

Fig. 2 is a block diagram illustrating a power regulator 1 applying the method of the invention to the ac power supply from the AC source AC to the load L by adjusting the phase angle of the AC voltage VAc. The power regulator 1 comprises a switching unit 2 and a control unit 3. The switching unit 2 has two MOSFET power transistors 21, 22 connected in series which operate as switching elements 10, k1, k2. In this embodiment, they are connected in series such that their source terminals S1, S2 are coupled together and further to the virtual ground VM of the power controller 1. Hereby, the drain terminal D1 of the first MOSFET transistor 21 is the input terminal of the switching unit 2 and is connected to an alternating current source AC. The drain terminal D2 of the second MOSFET transistor 22 is the output terminal of the switching unit 2 and is connected to the load L. Each MOSFET transistor includes an actual transistor switch corresponding to the switching element k1, k2 of the power regulator in FIG. a body diode dl, d2 disposed between the downstream hub S1, S2 and the drain hub D1, D2. The MOSFET transistors 21, 22 are applied to their gate terminals G1, G2 by the applied control voltages from the control unit 3 to an electrically conductive or closed state and a non-conductive or open state, respectively, during each supply voltage, i.e., alternating voltage VAC.

The control unit 3 comprises a semiconductor detector 4, a synchronization unit 5, a switching control unit 6, and a setting unit 7. The semiconductor detector 4 indicates the input; 25 positive PA and negative PB, respectively, of the alternating voltage VAc.

* The synchronization unit 5 detects a change in the direction of the load current IL, i.e. the zero point N1, N2, N3 of the current 1 # '·' (cf. Fig. 4a and 5a). The setting unit 7 determines the setpoint of the time delay. Synchronization unit 5 is connected to setting unit 7. Sync :, Cloning unit 5 informs setup unit 7 of the zero points N1, N2 ': 30 of the current IL and this is defined as the time delay or start time. The setting unit 7 is supplied with oh- '. : outside the sensing unit 3, the time delay ta setpoint that determines the load L feeds! electric power. The setting unit 7 is connected to the switching control unit 6, which. information is provided to the setting unit 7 as soon as the set time delay has been reached. The semiconductor detector 4 is also connected to the switching control unit 6. The semiconductor detector 4 provides the switching control unit 6 with information about the positive PA and negative PB of the alternating voltage VAC. Based on the information obtained from the switching control unit 6 from the half-sequence detector 4 and the setting unit 7, the MOSFET transistors 21, 22 acting as switching elements k1, k2 are controlled such that each transistor changes its state simultaneously; when one MOSFET transistor is directed to a conductive state, i.e. a closed state, the other is directed to a non-conductive or open state 5, as described in principle in connection with Figure 1 above.

A preferred control unit 3 of the power regulator 1 according to the invention is shown in Figure 3. Its implementation is as follows.

The semiconductor detector 4 is e.g. a level detector formed by a resistor 40 and a zener diode 41. The level detector is arranged to monitor the voltage between the input terminal of the power control unit 1 and 10 and the virtual ground VM. When the instantaneous value of the alternating voltage VAC rises above the zener voltage Vz of the zener diode 41, a substantially semiconductive positive voltage pulse, e.g., indicated as "1", is obtained at the output of the semiconductor detector. Hereby, there is a positive semiconductor PA of the alternating current source AC voltage VAc. In the negative half-cycle PB of the AC voltage 15 AC of the alternating current source 15, the voltage across the zener diode 41 is its forward threshold voltage VD, which is denoted, for example, as "0".

The synchronization unit 5 is a detector whose transistor 53 implementing an open collector output coupled to the first input of the setting unit 7 is in a non-conducting state ai-20 during the delay time. When the load current IL is off, almost all the AC voltage of the AC source AC is affected between the in and out ports of the power regulator. This voltage causes a current, depending on the polarity of the alternating voltage, to flow through either the diode 50 or 51 through the base resistor 55 to the base of the transistor 52, leading to the transistor 52; but into space. When transistor 52 is in conductive state, output from resistor 54; The flow of 25 current is blocked at the base of transistor 53, whereby transistor 53 is in a nonconductive state. With the load current IL connected, the voltage difference between the in and out ports of the controller is almost zero, whereby the base of transistor 52 is not energized and is conductive; in the dark. The current then passes through the pull-up resistor 54 to transistor 53! , 'On the base and transistor 53 is in a conductive state. Since the load current IL is always interrupted at its zero point, the break point also indicates zero N1, N2, N3.

1 I

The setting unit 7 includes an RC time constant circuit formed by an adjustable resistor 71 and a capacitor 72 and a comparator 73. When the load current IL is connected, the open collector output of the synchronous unit 5 holds the capacitor; V market 72 almost unreservedly. Immediately after the cut-off of load current II, the open collector output of the synchronization unit 35 enters a non-conductive state and the charge of the capacitor begins to increase as determined by the values of resistor 71 and capacitor 72. As the charge increases, the voltage across capacitor 72 also increases. When the voltage across capacitor 72 reaches the reference voltage level of comparator 73, the setting pulse occurs at the output side of comparator 73. The setting pulse is applied to the clock input CL of the D-flip 6 of the 5 control units.

The switching control unit 6 is preferably a flip-flop, especially a D-flip-flop. Its data input DI is connected to the output of the semiconductor detector 4 and its clock input CL to the output of the setting unit 7. When the setting pulse is supplied from the setting unit 7 to the clock input CL, the state information at the data input DI is transferred as such to the D-flipper output Q and inversely to the output 10Q. The D-flipper outputs Q and Q are connected via resistors 8 and 9 to their respective gates G1, G2. .

Resistors 8 and 9 set the switching speeds of the MOSFET transistors 21 and 22.

The electronic units 4, 5, 6,7 of the control unit 3 require their own power supply. The operating voltage V + is implemented e.g. with a suitable power supply known to those skilled in the art and not shown in the drawings. Generally speaking, the operating voltage V + is preferably formed by rectifying and filtering the AC voltage VACi

The power regulator 1 shown in Fig. 2 operates by resistive gain L in the same manner as the principle circuit of Fig. 1, which was described above with reference to Fig. 4. Thus, Figures 4b, 4c show the control voltages applied to the gates G1, G2 of the first and second MOSFET transistors 21, 22 as a function of time t, where, e.g., state "1" represents a suitable positive control voltage and state "0" -, · items such as virtual land VM.

Fig. 5 illustrates voltage and current curves in connection with the power regulator 1 of Fig. 1 '* 25. In this case, it is assumed in Fig. 5 that the load L is inductive. Fig. 5a shows a graph of the alternating voltage VAC :: from an alternating current source AC over several consecutive half-periods PA, PB, PA, ... as a function of time t.

Fig. 5b and 5c, respectively, show the state of the switching element k1 and k2, respectively, such that 0 represents the open position of the switch and 1 represents the closed state of the switch. These figures also show, in principle, the control voltages applied to the gates G1, G2 of the MOSFET transistor 21, 22 of Figure 2. The curve forms of the voltage VL applied over the load L and respectively: ': the current IL are shown in Figures 5d and 5e.

Next, the operation of the power regulator 1 of Fig. 2 in controlling an inductive load by nature will be described with reference to Fig. 5; 5a, 5b, 5c, 5d, 5e and FIG. 3. At time 9454588, the AC voltage of the alternating current source AC is at zero. At time B, the current throughput IL of the pair of MOSFET transistors 21, 22 stops from load L to the alternating current source AC because the diode d1 of the first MOSFET transistor 21 is blocked to the voltage across it, i.e., auto-commutation occurs.

5 Let be the load current IL at zero N1. It should be noted that due to its inductive nature, the load current IL is no longer in phase with the load voltage VL, but follows a voltage change with a delay. At time B, the synchronization unit 5 starts the set-up unit 7 and the semiconductor detector 4 directs the D-flip data input DI to the switch control unit 6 to state "1" because there is a positive semiconductor PA of AC voltage AC 10. At time C, the setting unit 7 supplies a setting pulse to the D-flip clock input CL and the D-flip Q output goes to "1" and the inverse Q output to "0" respectively. Through the body diode d2 of the MOSFET transistor 22, at time D, the AC voltage VAC of the alternating current source 15 reaches zero. There is a load current IL at zero N2, whereupon the synchronization unit 5 activates the setting unit 7 and the semiconductor detector 4 20 directs the switching control unit 6, i.e. the D-flip data input DI to "0", because the AC voltage VAC To D-flip clock input CL and D-flip Q output • _ goes to "0" and inverse Q output to "1". Now, the load L begins to flow through the current, passing the second conductor channel of the second MOSFET transistor 22 and the body diode d1 of the first MOSFET: \ 25 transistor 21 to the alternating current source AC.

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The voltage VAC of the AC source AC is at zero and the duty cycle starts again from time A to A = G. The next time H = B is again zero, at N3 = N1.

In the above embodiment of the invention, the switching unit 2 is formed by two MOSFET transistors 21, 22 connected in series. it is clear that MOSFET transistors are interchangeable with other series connected; power transistors, such as an IGBT transistor or a bipolar power transistor, which are accompanied by diodes d1, d2.

. The invention is not limited to the above exemplary embodiment, but many modifications are possible within the scope of the inventive idea defined by the claims.

Claims (9)

A method for adjusting the AC power supplied to a load by adjusting the phase angle of the AC voltage, wherein the switching unit (2) is comprised of two switching elements (k1, 5k2) connected to each other and a load (L), i.e., first and second switching elements , d2), the switching elements being actuated alternately to an electrically conductive and a non-conducting state during a half-cycle of an ac supply voltage (Vac), characterized in that the first semiconductor (PA) after the first load delay (IL) the switching element (k1) is directed to the conductive state while the second switching element (k2) is directed to the non-conducting state, wherein the load current (IL) is arranged to pass through the first switching element (k1) and the forward diode (d2). until the direction of the gate current (IL) changes at the second zero point (N2) of the current, whereby the direction of the load current (IL) is reversed with respect to the second diode (d2), thereby preventing current flow to the load; (IL) after the time delay (ta) determined from zero (N2), the second coupling element (k2) is guided to the conductive state while the first coupling element (k1) is guided to the non-conductive state; via the first diode (dl) until the direction of the gate current (IL) changes again at the next zero point of the current (N1, N3), whereby the direction of the load current (IL) reverses with the first diode (dl), thereby preventing current flow to the load , which corresponds to the first semester (PA), the above steps are repeated. Method according to Claim 1, characterized in that the successive half-cycles (PA, PB) of the alternating voltage (VAc) are monitored and determined by the positive and negative half-cycles by which the control of the switching elements (k1, k2) is implemented. ) directions. : 30 3. Power regulator (1) for adjusting the AC power supplied to the load (L) | by adjusting the phase angle of the alternating voltage, which power regulator comprises a switching unit (2) consisting of two switching elements (k1, k2) connected in series with each other and a load (L), i.e. the first and second switching elements and opposite diodes , d2), and 35 control units (3), by means of which the switching elements (k1, k2) are alternately controlled by 114588 during a semiconducting alternating voltage (Vac) applied to an electrically conductive and a nonconducting state, characterized in that the control unit (3) comprises: ), which detects a positive (PA) and a negative (PB) half cycle of the ac supply voltage; A switching control unit (6) for supplying information on the positive and negative half-cycles (PA, PB) of the alternating voltage (VAc), wherein the switching element (k1, k2) is selected and controlled into a conductive and a non-conducting state; - a synchronization unit (5) for detecting the moment of zero crossing of the load current (IL), i.e. the zero point (N1, N2); and 10. a setting unit (7) for providing synchronization from the zero (N1, N2) of the load stream (IL) to determine the start time of the time delay (s), and for setting the time delay (s) within the half-cycle (PA, PB); power supply to the load (L) is initiated by informing the time delay expiration of the switching control unit (6) arranged to switch either of the switching elements (k1, k2) to a conductive state depending on the current alternating voltage semiconductor (PA, PB); travel through one diode and one switching element (k1, d2; k2, d1); and wherein the power control interrupts the current supply to the load substantially: at the zero point (N1, N2) of the load current (IL) when the current direction reverses in the reverse direction of the diode (d2; d1):. Power regulator according to Claim 3, characterized in that the switching unit is • »'; ; the unit (2) is formed by two MOSFET transistors (21,: 22) connected in series. ) · Power regulator according to Claim 3, characterized in that the switching unit (2) is made of two power transistors connected in series, such as IGBT 'or bipolar transistors, which are accompanied by diodes (d1, d2). Power regulator according to Claim 3, 4 or 5, characterized in that the switching control unit (6) is a D-flip, the inverting outputs (Q, Q) of which are connected to the control of the first and second switching elements (k1, k2) respectively. -30 to us. Power regulator according to one of claims 3 to 6, characterized in that the semiconductor detector (4) is a level detector formed by a resistor 114588 (40) and a zener diode (41) arranged to monitor the power control unit (1) and the switching unit. (2) the voltage between the input terminal (in) and the virtual earth (VM). Power regulator according to any one of claims 4 to 7, characterized in that the synchronization unit (5) is a detector for detecting a change in the direction of the load current (II) from positive to negative and vice versa and informing the setting unit (7). Power regulator according to any one of claims 4 to 8, characterized in that the setting unit (7) is a timing circuit which is triggered by the change information received from the synchronization unit 10 and in which the time delay (s) is set externally by suitable control.