FI105621B - Method and apparatus for processing analog signal - Google Patents

Description

1 .Λ 105621

Method and apparatus for processing an analog signal

According to a first aspect, the present invention relates to a device for processing an analog input-signal, such as speech, which has a large amplitude variation and a first ratio of maximum and minimum amplitude, comprising a first ratio to a second ratio of square root of a first ratio. , and which gives an analog ratio output signal having a second ratio.

Also, according to a first aspect, the invention further relates to a method for processing an analog input signal such as speech having a wide range of amplitude and a first ratio of maximum and minimum amplitude, comprising the steps of reducing the first ratio to a second ratio of square root of first ratio; to provide an analog output signal having a second ratio.

Specifically, the purpose of said processing is to reduce the ratio of the maximum and minimum amplitude at the output of the processing to the square root of the pre-processing ratio so that said signal is better transmitted over a channel having a limited dynamic range under the effect of summing noise.

According to another aspect of the invention, the invention also relates to an apparatus and method for processing an input signal having a narrowed amplitude region to produce an output signal having an amplitude region squared. Specifically, said input signal may be a signal produced as an output signal according to the first aspect.

The quality of voice transmission in a communication network suffering from transmission noise, such as a radio link, can be described and measured by a signal-to-noise ratio (SNR). Since the amplitude of the actual 2 105621 speech signal is not constant but varies more or less randomly over a wide dynamic range, it is not a suitable test signal for performing SNR measurements. Instead, 5 standard tones of different frequencies in the frequency band are usually used for this purpose, and the result of the measurement is called the TTNR (Test Tone to Noise Ratio).

However, subjectively perceived speech quality is better described in terms of peak speech volume and noise during quiet periods, which is not measured by the TTNR. A better measure of subjective quality would be the ratio of the level of the activated test tone to the residual noise when the test tone is switched off. To optimize this important quality property of the subjective-15, techniques known to reduce dynamics are often used.

Narrowing involves adjusting the variable gain at the transmitting end adapted to either increase the transmission level during quiet periods and / or decrease the level during loud periods so that the entire dynamic range of the signal is narrowed (compressed, compassed) towards the mean. At the reception end of the extender. (expander, decompander) performs inverse scaling, increasing the level during loud cycles to restore the original deviation of the signal 25 and correspondingly decreasing the level during quiet periods. In the latter case, the summed noise in the transmission also decreases during quiet periods, just as is required to maximize the quality detected.

A commonly used attenuation law is the so-called square root law, where the amplitude of the signal actually transmitted is proportional to the square root of the amplitude of the source. For example, during a period in which the speech source signal has an instantaneous amplitude of 1/1000 by 35 units, the attenuator would increase the transmitted amplitude to 1/10.

3, 105621

Correspondingly, during a period where the source amplitude would be 9 units, the transmitted amplitude would be reduced to 3 units, while the unit-sized amplitude by definition is a constant 5 level in the attenuator. Now suppose that the noise summed in the transmission corresponds to 1/100 units of amplitude. During the silent period when 1/10 was transmitted, the received signal would comprise 1/10 units of the desired signal plus 1/100 units of noise. If the expander reduces the signal from 1/10 units to 10 at its original 1/100 units, the same law would reduce the noise from 1/100 to 1/10 000. In the case where the desired signal is at zero level, the attenuator would interpret the received 1/100 unit noise as a attenuated signal level and return it to the level at which it believed the original signal level was, namely, 1/10,000.

Thus, it can be seen that during quiet periods, the noise level at the output of the expander is the square of its value that it would otherwise have been without the use of reduction and expansion. .

S NR is often measured on a logarithmic decibel scale and defined as dBs = 20LOG (signal amplitude / noise amplitude) 25 «

If the average amplitude of the signal during active speech is taken as 1 and if the amplitude of noise during silent periods is equal to 1/100 without attenuation, then the SNR calculated by the above formula is 30 40 dB.

: When using narrowing / expanding, the noise of silent periods is reduced to 1 / 10,000, giving an SNR of 80 dB, representing a significant improvement in subjective quality.

4, 105621

In the two prior art methods for performing square root reduction, known as feed-forward and feedback methods, the reduced output signal is obtained by dividing the input signal by through.

The benefit of the feedback method is that the square root function is not explicitly required and also that the amplitude measurement is performed at a reduced output, which halves the signal range, expressed in dB, which the measuring device must process. The square root extension law 15 follows that the output amplitude is the input amplitude divided by the output amplitude.

There are two known embodiments of the latter type of constrictor. The first 'is a fully analog embodiment of a circuit in which the dividing circuit would in fact be implemented using an analog multiplier in the feedback loop. The second is a fully digital embodiment in which the input signal is first digitized using an analog-to-digital converter, then fed to a digital signal processing circuit which numerically implements a reduction or feedback type reduction algorithm. The result then has to be converted again to an analog signal using a digital-to-analog converter.

These two known forms of settlement have their own disadvantages. The downside to a fully analog system: * The need is for some components with tight tolerances that are difficult to fabricate into integrated semiconductor circuits. The downside to a fully digital embodiment is the need for quite sophisticated AD and DA converters 105621

D

and an expensive and power-consuming digital signal processor circuit.

It is an object of the present invention to provide a new way of implementing a square root law reducer 5 having the advantage that it can be more easily integrated into low cost silicon based integrated circuits using low cost semiconductor processes. This object is achieved by the apparatus and methods according to the first and second aspects of the present invention,

The apparatus of the first aspect of the invention comprises an analog-to-digital converter which converts said input signal to an integer stream. representing, in a non-zero manner, the instantaneous value of the input signal divided by the first reference voltage, means for generating the first reference voltage proportional to the amplitude of said output signal; a digital-to-analog converter which converts said 20th reading current back into an analog signal waveform with respect to a constant reference voltage, which analog waveform generates said output signal.

The method of the first aspect of the invention comprises the steps of converting said input signal to an integer current proportionally representing the instantaneous value of the input signal divided by a first reference voltage generated proportional to the amplitude of said output signal, converting said reading current to which analog waveform generates said output signal.

6 105621

A device according to another aspect of the invention comprises an analog-to-digital converter having a means for converting said input signal into an integer sequence proportionally representing said input signal, a digital-to-analog converter converting said number sequence back to an analog signal generating said output signal, an output signal relative to the reference voltage, 10 means for deriving said reference voltage based on the amplitude of said input signal.

The method of the second aspect of the invention comprises: steps for converting said input signal to an integer sequence which proportionally represents said input signal, converting said number sequence back to an analog signal generating said output signal by scaling said output signal with reference to a reference voltage derived from the amplitude of said input signal.

Embodiments of the present invention will be further described below with reference to the accompanying schematic drawings, in which Figures 1 and 2 are general block diagrams of two aspects of the present invention, Figures 3-8 schematically illustrate various circuit solutions of the blocks included in Figures 1 and 2; the decoder, respectively, Figs. 5 and 6 show a delta sigma or sigma-del tacoder and decoder, respectively, Fig. 7 illustrates narrowing using delta or delta sigma modulation having different steps, and i 9 105621 Fig. 8 illustrates an expansion, when using constant step encoding and variable step decoding.

Fig. 1 is a block diagram illustrating a device which processes an analog input signal S, such as speech, which has a large amplitude variation. This device is intended to reduce the ratio of the maximum and the minimum amplitude of the output signal P, after processing, to the square root of the ratio before processing, in order to better transmit said signal 10 through the effect of summing noise on a channel with a limited dynamic range.

The apparatus comprises an analog-to-digital converter 2, which is adapted to convert, as will be described further below, signal S to an integer stream. N1, N2, N3, ... 15 These numbers can have only two possible values in the boundary case, such as plus one and minus one. The numbers in this current represent, in some proportion, the instantaneous value of the input signal S divided by the reference voltage R. The smoothed amplitude measuring device 4 generates 20 of this reference voltage .

Figure 2 schematically shows a device which is complementary to the device shown in Figure 1 and which processes a signal U of reduced amplitude variation that the device of Figure 1 can produce. The device of Fig. 2 is intended to produce a signal V having amplitude-30 variation returned to a normal region which is a square of the narrowed region.

The apparatus comprises an analog-to-digital converter 8 which • converts said reduced input signal U into an integer sequence M1, M2, M3, ... These numbers can, in the boundary case 35, obtain only two possible values, such as plus one and? This number sequence represents the signal U in a proportional manner and is converted back to the analog signal V by the digital-to-analog converter 10. The converter 10 scales the output signal V with reference to the reference voltage 5 Q, which is derived by determining the amplitude of the input signal U with the measuring device 12, which may include smoothing the measured value by means of a low pass filter.

According to an important embodiment of the present invention, the technique 10 used in converters 2, 6, 8 and 10 may be of the type delta modulation, delta sigma modulation, or a variant thereof.

The delta modulation encoder digitizes the analog signal into a sequence of 1-bit binary numbers representing +1 or -1. These values are used to change the direction of the embedded function 15 generator, i.e. the integrator, so that it rises if the previous value was less than the output signal, or decreases if the previous value was too large. The amount by which the integrator rises or falls between samples is called a step. If 1-bit samples 20 are generated at too high a frequency, the steps required to monitor signal change at a given frequency must be smaller, and thus the step-wise approximation of the waveform of the signal is more accurate. The roughness of this 1-bit quantization can thus be compensated by increasing the bit rate of the 25 bar sample sufficiently to achieve the desired accuracy.

Fig. 3 shows an integrator 14 whose output signal is compared to an input signal S in a comparator 16. Decision D is performed at a specific bit rate Fb by clock-30 by locking circuit or flip-flop 18 at rising edges of a clock signal having frequency Fb. The clocked decision • 'is then fed to the switch 20 to select the direction to which the integrator 14 is directed during the next sample cycle. The magnitude of the change is determined by the value STEP.

't .J k-. J

9 105621

In another known system, the STEP value is incremented each time the integrator is steered in the same direction three times in a row, which indicates that the signal change rate is greater than 5 that the integrator can follow at the current STEP. This known system is called "reduced delta modulation" and also called CVSD (Continuously Variable Slope Delta).

As shown in Figure 4, the delta modulation is reconverted to an analog signal by feeding it to an integrator 22 similar to that used in the encoder.

The difference between the encoder integrator 14 and the rebuild integrator 22 is that the latter must contain some form of leakage component 15, for example a leakage resistor 24 coupled to the integrator capacitor 26, to determine an arbitrary integrator time constant to be zero (i.e., arbitrary boot state will disappear over time).

After reconfiguration by the leakage integrator, the high-frequency quantization noise can still be reduced by a low-pass filter which emits the highest probable signal frequencies, but which attenuates the noise frequencies in the sample bit rate and up to 25 low frequencies.

The use of a related algorithm known as sigma-delta or clelta-sigma modulation is illustrated in Figures 5 and 6. The difference is that the input signal S is applied before the integrator, denoted 22 'here, instead of being applied 30 . Compared to delta modulation, * the signal is subjected to additional integration in the encoder.

6, which is then eliminated in the decoder shown in Figure 6 by omitting the rebuilding integrator 22 and using only low pass filtering at 35 '. Delta sigma modulation represents values between + ASKEL and L J U Λ 105621 ASKEL by alternating between them in the correct average ratio and in this respect is similar to pulse width modulation.

Delta or delta sigma modulation schemes may also include more than one integrator or other frequency response modulation in the feedback loop, and the signal may or may not pass through one or more such components. It is also possible to construct delta modulation encoders and decoders 10 in which the error between the value provided by the integrator and the value of the input signal is quantized by more than one bit, and then the modulation method is known as delta PCM.

The details of the structure of all such variations need not be explained herein, as they can be found in the technical literature. Any structure characterized by an encoder which digitizes an input signal using a scale defined by a STEP value or a similar reference voltage which may be varied according to the signal, and which digitized signal can be easily converted back to an analog signal using either the same or a different constant step or variable step or reference voltage may be suitable for carrying out the present invention.

Both variable and constant steps can be used in connection with the present invention. If a signal is decoded using a small step and decoded using a large step, its amplitude will be increased. If the coding step is larger than the decoding step, the amplitude decreases. Thus, if the encoding step changes while keeping the decoding step constant, the output level of the signal is inversely proportional to the step, thus accomplishing the division function required by the square root taper.

Therefore, it is only necessary to make the step proportional to the reduced amplitude of the output signal by deriving it from the amplitude measurement shown in FIG. 7.

U 105621

FIG. 7 illustrates by way of example an encoder 30 of the delta or delta sigma type and employing 1-bit quantization, then the constant step decoder is simply a low pass filter 32. The variable as-5 decoder is derived by measuring at 34 the re- signal amplitude. The amplitude measurement value is further influenced by the low pass filtering function, i.e. the smoothing time constant 36, which is called the reduction time constant. This is defined in various international standards that use attenuation in · speech transmission.

The corresponding expander circuit is shown in Fig. 8. In this case, the reduced input signal is encoded in 38 constant steps to convert it to digital 15, then encoded in 40 back to analog format using a variable input proportional to the smoothed input amplitude. In order to validate the system performance, the low pass filter, i.e. the time constant used at 42 to equalize the amplitude measurement value at the extender 20 at 44, should be the same as that used in the attenuator.

t

Claims (12)

An apparatus for processing an analog input signal (S) whose amplitude varies considerably, such as number, and having a first ratio of maximum to minimum variations, including means for reducing the first ratio to a second ratio, which is the square root of the first ratio, and for the output of an analog output signal · (P) exhibiting the second ratio, characterized by an analog-to-digital converter (2) for changing said input signal into a stream of integers (N1 , N2, ...) representing proportionally the instantaneous value of the input signal (S) divided by a first reference voltage (R), means (4) to generate the first reference voltage in proportion to the amplitude of the output signal ( P) a digital-to-analog converter (6) for re-converting the speech stream into an analog signal form in proportion to a constant reference voltage, which analog path form forms the output signal (P). 2. Device according to claim 1, kä. The net sign is that the integers consist of only two possible values such as plus 1 and minus 1. Device according to claim 1 or 2, characterized in that the first reference voltage (R) is generated by a smoothed amplitude measuring device (4). Device according to any one of claims 1-3, characterized in that the analog-to-digital converter (2) comprises an encoder (14-20; 30) operating according to a technique known as delta modulation, delta gamma modulation. or variants thereof, which encoder has means for quantizing the input signal (S) to a resolution of only one binary bit, means for obtaining a desired accuracy by increasing the sampling rate or bit rate, means (20) for determining the step size of the encoder in response to the first reference voltage, which digital-to-analog converter (6) has a decoder for the quantized signal, which is operated at a constant step size. Apparatus for processing an input signal (U) with compressed amplitude range in order to generate an output signal (V) with an amplitude range constituting the square of the compressed area, characterized by - an analog-to-digital converter (8) with means to change the input signal to a sequence of integers (M1, M2 ...), which result in a proportional. method, the input signal represents a digital-to-analog converter (10) for converting the speech sequence back into an analog signal forming the output signal (V), which converter has means for scaling the output signal in proportion to one. reference voltage (Q), means for deriving the reference voltage in response to the amplitude of the input signal. Device according to claim 5, characterized in that the sequence of integers is limited to only two possible values such as plus 1 and minus 1. Device according to claim 5 or 6, characterized in that the amplitude of the input signal is determined by a measuring device (12) comprising a low-pass filter for smoothing the measurement. Device according to any one of claims 5-7, characterized in that the analog-to-digital converter (8) and the digital-to-analog converter (10) comprise an encoder and a transducer respectively. a decoder operating in accordance with a technique known as delta modulation, delta sigma modulation or variants thereof, which encoder has means for generating said output number sequence as containing a single bit binary representing only two possible values, and in a proportion non-linear means representing the instantaneous value of the input signal (U), means for compensating the coarse cross-quantization obtained thereby, by increasing the sample conversion rate or bit rate to obtain a desired accuracy, which decoder is arranged to accept output bitstream generated by the encoder and converting it back to an analog signal path shape, and having means for generating said output signal by scaling the analog path shape in proportion to the reference signal using the latter to determine the decoder step size. A method of processing an analog input signal (S) whose amplitude varies considerably, such as tai, and having a first ratio of maximum to minimum variations, including reducing the first ratio to a second ratio, which is the square root of the first ratio, and output of an analog output signal (P) exhibiting the second ratio, characterized by changing said input signal to a stream of integers representing proportionally the instantaneous value of the input signal. divided by a first reference voltage, generated in proportion to the amplitude of the output signal, the conversion of the speech current into an analog 19. 105621 signal form in proportion to a constant reference voltage, which analog path form forms the output signal. 10. A method according to claim 9, characterized in that the integer consists of only two possible values such as 5 plus 1 and minus 1. 11. A method for processing an input signal with compressed amplitude range in order to generate an output signal. having an amplitude range constituting the square of the compressed range, characterized by changing the input signal into a sequence of integers, which sequence proportionally represents the input signal, converting back the speech sequence into an analog signal forming the output signal, during scaling the output signal in proportion to a reference voltage derived in response to the amplitude of the input signal. 12. A method according to claim 11, characterized in that the sequence of integers is limited to only two possible values such as plus1 and minus 1. »f