FI101180B - Addressing method in a signal processor and peripheral circuit which can be used in the addressing process - Google Patents

Description

101180

The invention relates to an addressing method in a signal processor according to the preamble of claim 1.

The invention also relates to a signal processor peripheral circuit suitable for the assignment method.

10

In high-speed signal processors, which typically have an operating cycle length of the order of 25 to 50 ns, the use of external data memory or external registers often requires waiting periods because the processor's paging time requirements for allocating external memory are too stringent. However, in a signal processor program that performs real-time signal processing, each waiting period is too long and should be eliminated.

20 In many signal processors, the most efficient computation requires indirect assignment for use in memory addressing. Memory is thus implicitly referred to as the so-called through the index register. As the memory reads or writes to the memory, the index register may be updated to indicate the memory location required in the next instruction. However, the upgrade usually cannot be arbitrary and there are only a limited number of options available. Typically, the value of an index register can be either increased or decreased by one, the value kept constant, or the value of another register added to the index register. For example, in the case of an AT&T DSP1610 processor:

aO = * rO / * register aO reads register rO

from the address specified by the content, rO 35 does not change * /

aO = * rO ++ / * register ao reads register rO

from the address specified by the contents, rO changes to rO = rO + l for the next indirect 2 101180 operating cycles * / aO = * rO— / * register aO is read from the address determined by the contents of register ro, rO changes to rO = rO-1 for the next indirect 5 operating cycles * /

aO = * rO ++ j / * register aO reads register rO

from the address determined by the content whether it changes to rO = rO + <j> for the next indirect operation period * / 10 Due to these limitations, unnecessary instructions are often added to the signal processor program to set the index register to indicate the next required memory location.

15

The signal processor is often used in conjunction with various peripheral circuits, e.g., an ASIC circuit, which acts as an aid to the signal processor, performing those functions that are ill-suited to be calculated by the signal processor.

20 The signal processor and the peripheral typically communicate via registers on the peripheral that appear in the processor's external data storage space. In this case, in order to enhance the cooperation between the signal processor and the peripheral circuit, a method is needed which avoids waiting periods in the signal processor and minimizes unnecessary updates of the index registers. With current technology, the most demanding real-time signal processing tasks have not been possible.

The object of the present invention is to eliminate the shortcomings of the above-described technique and to provide a completely new type of assignment method in a signal processor and a signal processor peripheral circuit suitable for the assignment method. Both direct and indirect addressing can be used in a signal processor program using the invention.

The invention is based on the fact that the memory addresses of the peripheral circuit are proactively assigned so that in the operating period N

3 The peripheral address required for 101180 is given during one of the preceding operating periods.

More specifically, the method 5 according to the invention is characterized by what is set forth in the characterizing part of claim 1.

The peripheral circuit according to the invention, in turn, is characterized by what is set forth in the characterizing part of claim 6.

The invention provides considerable advantages.

The signal processor can assign even slow ASIC or muis-15 circuits without timing problems or wait periods in situations where traditional solutions necessarily require wait periods. Unnecessary index register updates are omitted when using the conversion table. By means of the invention, it is possible to use a full clock frequency for the signal processor 20 and yet to perform tasks suitable for peripheral circuits without memory assignment problems, whereby a speed optimizer can be implemented for signal processing. In this way, in fast signal processing applications, for example, digital filters can be implemented at a speed that has not previously been possible.

The invention will now be examined in more detail with the aid of exemplary embodiments according to the accompanying figures.

30

Fig. 1a shows a block diagram of a signal processor and its peripheral circuit which can be used in connection with the invention.

Fig. Ib shows in a more detailed block diagram the peripheral circuit according to the invention illustrated in Fig. 1a.

Figure 2 shows a timing diagram according to the prior art.

Figure 3 shows a timing diagram according to the invention.

Figure 1a illustrates a device environment in which the invention can be used. The apparatus consists of a signal processor 20 and a peripheral circuit 21 connected thereto via the address bus 1 and the data bus 11.

According to Fig. 1b, the memory registers 9 and 10 of the peripheral circuit 21 are assigned via the address bus 1. From the point of view of the signal processor, the registers 9 are read registers and the registers 10 are write registers. Through the address buffer 2, the row-shaped addresses are directed to a conversion table 15 3, which can be controlled and updated if necessary by an external input 15. Alternatively, the conversion table 3 can be controlled via the data bus 11, whereby some of the registers 10 contain a conversion table. After the conversion table 3, the entered address is transferred to the address register 4, 20 followed by the address decoding block 5. In this application, based on the conversion table 3, the address of the address bus 1 informs the control logic 6 whether it is a read or write operation. If the conversion table is omitted, the type of operation is already seen in the address-25 path of the address bus l. Information on whether this is a read or write operation can also be provided by a separate signal processor signal (R / W). This signal can be comprised as a single address bus 1 signal. Thus, the decoding block 5 controls the output controller 7 of the peripheral circuit and the input controller 30 8. Read registers 9 are connected to the output controller 7 and write registers 10 are connected to the input controller 8, respectively. The three-mode buffers, in turn, are controlled by the write / read mode 35 (r / w) control logic 6, which receives the direction information of the operation from the decoding block 5 and the signal processor of the block selection line 12 and the clock line 13.

5 101180

According to Fig. 2, in the prior art assignment, the read operation of the processor controlled by the block selection line 12 causes the data at the assigned address to be transferred to the data bus 11 only at the end of the operation period. Address-5 to bus 1, in turn, transfers memory address information with a very small delay. The operation of the peripheral circuit is synchronized by the clock and 13. The solution of the figure uses one waiting period (W = 1). Thanks to the waiting period, the data transmitted to the data bus 11 at the end of the reading period can be read. Using the wait period 10 slows down the device.

In the example according to Figure 3, four full operating cycles 31 to 34 and one incomplete operating cycle 35 are described. According to the invention, in the operating cycle 31 the address of the register required in the operating cycle 32 is transferred to the address bus 1 15. In the operating cycle 33, the signal processor 20 writes information to the data bus 11, which the peripheral device 21 reads at the end of the reading section of the operating cycle 33 20. It can be seen from the timing that the write operation is not particularly critical in terms of timing because the write takes place at the end of the write operation of the operating cycle 33. The write operation period 33, in turn, indicates an address to be read by the read operation period 34, the contents of which are available on the data bus at the beginning of the operation period 34. Likewise, operation period 34 indicates an address to be read in operation period 35.

The timing line "latch addr in" in Figure 3 depicts the time-30 moments at which the address information is transferred to block 2 of Figure Ib. The timing line "latch data out" in turn depicts the times at which the data corresponding to the address information is transferred from the peripheral circuit to the data bus 11. The timing line "latch data in" describes the time at which the information on the data bus 11 is transferred to the peripheral circuit 21 and the bottom line describes the times at which the address information is transferred from the conversion table 3 to the address register 4.

6 101180

Methodically, the solution according to the invention presented above is implemented by using the so-called in the assignment of the read registers 9 and the write registers 10 of the peripheral circuit 21. a predictive address; and an address conversion table 3. A forward-facing address means that in each instruction 31-35, which refers to registers 9 and 10 of the peripheral circuit 21, an address is given to the register used in the next instruction and not to which reference is now intended. In this case, there is no need to use waiting periods in the processor 20.

10

By means of the conversion table 3, the peripheral circuit registers 9 and 10 (M and N pieces) can be arranged in the memory space of the processor in an arbitrary order and even so that the same register is displayed at several different addresses. In this way, the registers of the different peripheral circuits in each application program can be obtained in optimal locations, whereby the number of unnecessary updates of the index registers can be minimized in the program.

20 Proactive assignment can only be used at the lowest program level. If a higher-level program also used proactive assignment, the interrupt program would mess up higher-level addresses. Therefore, if the upper level registers are to use the same peripheral registers as in the interrupt-25 program, the upper level assignment must use the usual unforeseen assignment and wait periods. Thus, a mechanism for moving from one form of address to another is needed.

30 Separate areas of the address space can be reserved for different address formats. In this case, the predictive assignment can be implemented so that it starts as soon as it is assigned to the memory block allocated to it. The termination of the predictive assignment, on the other hand, is done by pointing to a specific termination address or address range. Normal assignment does not require any start or stop operation, but it will not work unless the predictive assignment is turned off. The change of the assignment form can also be done on a separate signal line.

7 101180

The following is an example of a program using predictive assignment and conversion table in the case of the above-mentioned AT&T DSP1610 processor. Assume that the peripheral circuit has e.g. 8 registers RegO, Reg2, ..., Reg7.

5 These registers appear in the memory space of the processor, eg at addresses 0x2000-0x200f. The order of the registers is determined by the conversion table. The first memory location C (0) in the conversion table indicates which register appears at address 0x2000, the second memory location C (l) indicates which register 10 appears at address 0x2001, etc. Number 0 in the conversion table means register RegO, number 1 in register Regl, etc. Chapter 15 in the conversion table means end address to which writing stop using the proactive display format. The predictive addressing format starts when 15 is addressed to any of the addresses 0x2000 ... 0x200f.

Memory space seen by the processor

Conversion table i i |

Address Register C (0) = 15 0X2000

20 C (1) = 0 0x2001 RegO

C (2) = 3 0x2002 Reg3 C (3) = 7 0x2003 Reg7 C (4) = 15 0X2004 • · · 25 C (15) = 15 0x200f

The following program sequence calculates the sum of registers RegO, Reg3, and Reg7 twice. Each row in the left column represents one run. The start and end of the predictive indication is shown. The initialization of the conversion table is not shown. Registers j, rO, aO, and ai are internal registers of the processor.

35 8 101180 1 j = -2 / * Initialize offset register j * / 2 r0 = 0x2001 / * RegO address of register to register rO * / 3 aO = * rO ++ / * Read garbage, enter RegO address * / / * Start predictive indication, unless * / / * it is already running * / 5 4 aO = * rO ++ / * Read the contents of RegO received on the data bus in the previous operating period in register aO, give the address of Reg3 for the next (line 5) preliminary operating period * / 5 a1 = * r0 ++ j / * Read Reg3, enter the address of Reg7 for the next (line 7) reading period * / 6 aO = aO + a1 / * Calculate Reg0 + Reg3 * / 7 a1 = * r0 ++ / * Read Reg7 , enter the address of Reg0 for the next reading period (line 9) * / 8 a0 «a0 + a1 / * Calculate Reg0 + Reg3 + Reg7 * / 10 9 a0 = * r0 ++ / * Read RegO, enter the address of Reg3 as follows ( line 10) for the reading period * / 10 a1 = * r0 ++ / * Read Reg3, give the address of Reg7 for the next (line 12) reading period * / 11 a0 = a0 + a1 / * Calculate Reg (HReg3 * / 12 a1 = * r0 / * Read Reg7, give end address * / 15 13 a0 = a0 + a1 / * Read aan Reg0 + Reg3 + Reg7 * /

The following table illustrates, by way of example, the contents of the peripheral data and address buses on command lines 3, 4, 5, and 7 of the above program.

20 Command a0 = * r0 ++ a0 = * r0 ++ a0 = * r0 ++ j a1 = * r0 * +

The goal is to start the read + next- as above as in the above-indicated indicative operation section, transferring the required address to the address bus at the beginning of the next operation period

Address bus 0 * 2001 0 * 2002 0 * 2003 0 * 2001 (= reg0 address (= reg2 address) (= reg7 address) (= reg0 address) te)

Data bus XX RegO contents reg3 contents reg7 contents 25 The term "memory" in this context means registers, batteries or other memory means for storing data.

Claims (5)

9 101180 An addressing method in a signal processor apparatus comprising a signal processor (20) and a peripheral device (21) connected thereto via a data (11) and an address bus (1), the method by the signal processor (20) assigning memory addresses of the peripheral devices N (31-35) for transferring content to the data bus 10a (11) for use by the signal processor (20), and in operation N the memory of the peripheral device (21) for use by the processor (20) is proactively allocated in one operation period N to obtain the contents of the memory on the data bus (11) at the beginning of operation period N15, known that the memory of the peripheral device (21) is assigned via a separate conversion table (3) and the peripheral device (21) is directed to the predictive mode by assigning a first predetermined memory address area or address and out of the predictive mode 20 by assigning a second predetermined memory address range or address. Method according to Claim 1, characterized in that the peripheral device (21) is controlled to a predictive mode by a separate signal line (15). A peripheral device (21) in a signal processor apparatus comprising a signal processor (20) and a peripheral device (21) connected thereto via a data (11) and address bus (1), characterized in that the peripheral device (21) comprises predictive addressing means (2, 3) , 4, 5, 6) to proactively assign a memory (9, 10). A peripheral device according to claim 3, characterized in that it comprises means (2, 3, 4, 5, 6) for moving the peripheral device (21) into and out of the intended mode of operation. 10 101180 Peripheral device according to Claim 3 or 4, characterized in that the conversion table (3) comprises its own control line (15) for updating the content of the conversion table (3). 11 101180